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8 results
LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE
App. 2022026698
Filed 2022-04-28
RO PROCESSING COMPLETED-PLACED IN STORAGE
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OFFSET VERTICAL INTERCONNECT AND COMPRESSION POST FOR 3D-INTEGRATED ELECTRICAL DEVICE
App. 2022019082
Filed 2022-03-07
RO PROCESSING COMPLETED-PLACED IN STORAGE
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OFFSET VERTICAL INTERCONNECT AND COMPRESSION POST FOR 3D-INTEGRATED ELECTRICAL DEVICE
App. 17/686,692
Filed 2022-03-04
Patented Case
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LOW-STRESS DIELECTRIC LAYER, PLANARIZATION METHOD, AND LOW-TEMPERATURE PROCESSING FOR 3D-INTEGRATED ELECTRICAL DEVICE
App. 17/361,859
Filed 2021-06-29
Patented Case
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OFFSET VERTICAL INTERCONNECT AND COMPRESSION POST FOR 3D-INTEGRATED ELECTRICAL DEVICE
App. 63/159,749
Filed 2021-03-11
Provisional Application Expired
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CONTROLLING THE STOICHIOMETRY AND DOPING OF SEMICONDUCTOR MATERIALS
App. 14/615,068
Filed 2015-02-05
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
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PROCESS FOR COMBINED STOICHIOMETRY CONTROL AND DOPING OF II-VI SEMICONDUCTORS AND ALLOYS AT HIGH TEMPERATURES
App. 62/065,083
Filed 2014-10-17
Provisional Application Expired
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Process for Combined Stoichiometry Control and Doping of II-VI Semiconductors and Alloys at High Temperatures
App. 61/936,525
Filed 2014-02-06
Provisional Application Expired
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