Patent Assignment
Reel/Frame 011881/0016
Assignment of Assignor's Interest
Recorded: 2001-06-07
Received: 2001-06-14
Pages: 2
Assignors
CHUANG, CHEIN-HUI
Executed: 2001-05-13
KER, MING-DOU
Executed: 2001-05-13
LO, WEN-YU
Executed: 2001-05-13
Assignee
SILICON INTEGRATED SYSTEMS CORPORATION
SCIENCE-BASED INDUSTRIAL PARK, NO. 16, CREATION RD. 1, HSIN-CHU, TWX, R.O.C, TAIWAN
Covered Property
(1)
Esd Protection Circuit for Mixed-Voltage I/O by Using Stacked Nmos Transistors with Substrate Triggering Technique
Application:
09/874,996 →