IP Library › Granted Patent US 6,657,835
Granted Patent Utility
US 6,657,835 · Confirmation No. 5534

ESD PROTECTION CIRCUIT FOR MIXED-VOLTAGE I/O BY USING STACKED NMOS TRANSISTORS WITH SUBSTRATE TRIGGERING TECHNIQUE

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 Code Description Pages PDF
2011-05-10 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2011-05-10 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2010-03-26 PA.. Power of Attorney 2 View
2010-03-26 N417 Electronic Filing System Acknowledgment Receipt 2 View
2010-03-26 R3.73 Assignee showing of ownership per 37 CFR 3.73 1 View
2010-02-22 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2010-02-22 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2009-11-24 PA.. Power of Attorney 2 View
2009-11-24 N417 Electronic Filing System Acknowledgment Receipt 2 View
2009-11-24 R3.73 Assignee showing of ownership per 37 CFR 3.73 1 View
2008-04-08 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2008-02-22 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2003-10-03 IFEE Issue Fee Payment (PTO-85B) 1 View
2001-06-07 TRNA Transmittal of New Application 3 View
2001-06-07 SPEC Specification 8 View
2001-06-07 CLM Claims 3 View
2001-06-07 ABST Abstract 1 View
2001-06-07 DRW Drawings-only black and white line drawings 8 View
2001-06-07 OATH Oath or Declaration filed 3 View
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Quick Facts
Patent No.
US 6,657,835
App. No.
09/874,996
Filed
2001-06-07
Granted
2003-12-02
Pub. No.
US20020159208A1
Art Unit
2836
PTA
0 days