Patent Assignment
Reel/Frame 011915/0953
Assignment of Assignor's Interest
Recorded: 2001-04-13
Pages: 4
Assignors
KHARE, MANOJ
Executed: 2001-03-29
BRIGGS, FAYE
Executed: 2001-04-01
KUMAR, AKHILESH
Executed: 2001-03-29
LOOI, LILY PAO
Executed: 2001-04-02
Assignee
INTEL CORPORATION
220 MISSION COLLEGE BLVD., SANTA CLARA, CALIFORNIA, 95052
Covered Property
(1)
Method and Apparatus for Reducing Memory Latency in a Cache Coherent Multi-Node Architecture