Patent Assignment
Reel/Frame 012423/0633
Assignment of Assignor's Interest
Recorded: 2001-12-26
Pages: 2
Assignors
MUN, JAE KYOUNG
Executed: 2001-12-18
KIM, HEA CHEON
Executed: 2001-12-18
LIM, JONG WON
Executed: 2001-12-18
Assignee
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
161, KAJONG-DONG, YUSONG-GU, DAEJON-SHI, KOREA, REPUBLIC OF
Covered Property
(1)
Method of Manufacturing a Self-Aligned Gate Transistor with P-Type Impurities Selectively Implanted Below the Gate, Source and Drain Electrodes
Related Assignments
(5)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of One Half (1/2) of All of Assignors' Right, Title and Interest
Nov 3, 2009
From: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: IPG ELECTRONICS 502 LIMITED
Reel/Frame 023456/0363 →
Assignment of Assignor's Interest
Jul 23, 2012
From: IPG ELECTRONICS 502 LIMITED; ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
To: PENDRAGON ELECTRONICS AND TELECOMMUNICATIONS RESEARCH LLC
Reel/Frame 028611/0643 →
Assignment of Assignor's Interest
Feb 14, 2018
From: PENDRAGON ELECTRONICS AND TELECOMMUNICATIONS RESEARCH LLC
To: UNILOC LUXEMBOURG S.A.
Reel/Frame 045338/0797 →
Assignment of Assignor's Interest
Jul 12, 2018
From: UNILOC LUXEMBOURG S.A.
To: UNILOC 2017 LLC
Reel/Frame 046532/0088 →
Assignment of Assignor's Interest
Sep 9, 2021
From: UNILOC 2017 LLC
To: ATREUS LABS LLC
Reel/Frame 057453/0790 →