Patent Assignment
Reel/Frame 012429/0477
Assignment of Assignor's Interest
Recorded: 2002-01-03
Received: 2002-01-10
Pages: 2
Assignor
SATO, HIROSHI
Executed: 2001-12-12
Assignee
FUJITSU LIMITED
NAKAHARA-KU, KAWASAKI-SHI, 1-1, KAMIKODANAKA, 4-CHOME, KANAGAWA 211-8588, JPX, JAPAN
Covered Property
(1)
Method for Layout Design and Timing Adjustment of Logically Designed Integrated Circuit
Application:
10/033,938 →