Granted Patent
Utility
US 6,687,890
· Confirmation No. 8985
METHOD FOR LAYOUT DESIGN AND TIMING ADJUSTMENT OF LOGICALLY DESIGNED INTEGRATED CIRCUIT
Inventor:
Hiroshi Sato
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-12-16 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-01-03 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-01-03 | SPEC |
Specification | 17 | View | |
| 2002-01-03 | CLM |
Claims | 8 | View | |
| 2002-01-03 | ABST |
Abstract | 1 | View | |
| 2002-01-03 | DRW |
Drawings-only black and white line drawings | 11 | View | |
| 2002-01-03 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Hiroshi Sato
Kawasaki, JAPAN
Attorneys & Agents of Record
Classification
USPC
716/10
G01R31/318583
G06F30/39
G06F2119/12
G06F30/327
Prosecution
- Examiner
- LIN, SUN J
- Art Unit
- 2825
- Customer No.
- 21171
- Docket No.
- 1093.1047
- Confirmation No.
- 8985
Foreign Priority
2001-114709
·
2001-04-13
·
JAPAN
Publication
- Pub. No.
- US20020157074A1
- Pub. Date
- 2002-10-24
Patent Term Adjustment
0days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2015-04-27
CHANGE OF NAME
Recorded 2010-07-27
from
FUJITSU LIMITED
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2008-12-10
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Quick Facts
- Patent No.
- US 6,687,890
- App. No.
- 10/033,938
- Filed
- 2002-01-03
- Granted
- 2004-02-03
- Pub. No.
- US20020157074A1
- Examiner
- LIN, SUN J
- Art Unit
- 2825
- PTA
- 0 days
External Links