Patent Assignment
Reel/Frame 021985/0715
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2008-12-10
Received: 2008-12-15
Pages: 17
Assignor
FUJITSU LIMITED
Executed: 2008-11-04
Assignee
FUJITSU MICROELECTRONICS LIMITED
7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU, TOKYO 163-0722, JPX, JAPAN
Covered Applications
(100)
METHOD AND PROGRAM FOR FILE INFORMATION WRITE PROCESSING
App. No. 12/212,439
→
RADIO APPARATUS AND ANTENNA THEREOF
App. No. 12/198,271
→
Simulation of program execution to detect problem such as deadlock
App. No. 12/213,871
→
Simulation device for co-verifying hardware and software
App. No. 12/155,002
→
SYMBOL TIMING RECOVERY CIRCUIT
App. No. 12/112,757
→
CACHE COLORING METHOD AND APPARATUS BASED ON FUNCTION STRENGTH INFORMATION
App. No. 12/078,650
→
METHOD AND APPARATUS FOR LOGIC EQUIVALENCE VERIFICATION, AND COMPUTER PRODUCT
App. No. 12/081,127
→
METHOD FOR LAYING OUT DECOUPLING CELLS AND APPARATUS FOR LAYING OUT DECOUPLING CELLS
App. No. 12/078,341
→
DATA TRANSFER CONTROL APPARATUS AND DATA TRANSFER CONTROL METHOD
App. No. 12/057,533
→
MICROPROCESSOR SAVING DATA STORED IN REGISTER AND REGISTER SAVING METHOD
App. No. 12/076,857
→
LOGIC VERIFICATION METHOD
App. No. 12/076,552
→
FAILURE DIAGNOSTIC APPARATUS, FAILURE DIAGNOSTIC SYSTEM, AND FAILURE DIAGNOSTIC METHOD
App. No. 12/051,412
→
IMAGE RECOGNITION DEVICE AND IMAGE ROTATING METHOD
App. No. 12/050,513
→
IEEE 1394 TRANSMITTER, IEEE 1394 RECEIVER AND AUDIO DATA CONTENT TRANSMISSION METHOD
App. No. 12/046,684
→
Method and apparatus for measuring distance with graphic data
App. No. 12/073,897
→
DATA PROCESSOR AND MEMORY READ ACTIVE CONTROL METHOD
App. No. 12/040,269
→
SIMULATION METHOD AND SIMULATION APPARATUS
App. No. 12/037,297
→
SEMICONDUCTOR DEVICE AND DMA TRANSFER METHOD
App. No. 12/037,109
→
ASYNCHRONOUS CIRCUIT LOGICAL VERIFICATION METHOD, LOGICAL VERIFICATION APPARATUS, AND COMPUTER READABLE STORAGE MEDIUM
App. No. 12/036,516
→
COMPUTER SYSTEM AND MEMORY SYSTEM
App. No. 12/036,634
→
Computer-readable recording medium recording file processing program, and file processing method and apparatus, and computer-readable recording medium recording functional program
App. No. 12/071,715
→
PROCESSING APPARATUS FOR STORING BRANCH HISTORY INFORMATION IN PREDECODE INSTRUCTION CACHE
App. No. 12/071,586
→
PROFILING APPARATUS AND PROFILING PROGRAM
App. No. 12/033,975
→
PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME
App. No. 12/033,969
→
SIMULATOR ENGINE DEVELOPMENT SYSTEM AND SIMULATOR ENGINE DEVELOPMENT METHOD
App. No. 12/068,122
→
METHOD OF SEARCHING FOR WIRING ROUTE INCLUDING VIAS IN INTEGRATED CIRCUIT
App. No. 12/068,034
→
TIMING VERIFICATION METHOD AND APPARATUS
App. No. 12/010,202
→
Method of designing semiconductor integrated circuit, design device, and CAD program
App. No. 12/005,616
→
Semiconductor apparatus and buffer control circuit
App. No. 12/005,617
→
Secure processor system without need for manufacturer and user to know encryption information of each other
App. No. 12/004,423
→
OFDM RECEIVER APPARATUS
App. No. 11/958,579
→
TRANSMISSION MODE/GUARD LENGTH DETECTION CIRCUIT AND METHOD THEREFOR
App. No. 11/948,111
→
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PRODUCT
App. No. 11/946,467
→
METHOD AND APPARATUS FOR CHECKING CURRENT DENSITY LIMITATION
App. No. 11/979,834
→
INFORMATION PROCESSING APPARATUS PLAYING ENCRYPTED CONTENT DISTRIBUTED THROUGH NETWORK
App. No. 11/976,764
→
MOTION VECTOR DETECTING APPARATUS AND MOTION VECTOR DETECTING METHOD
App. No. 11/907,701
→
Information processing apparatus
App. No. 11/907,617
→
TIMING VERIFICATION METHOD AND TIMING VERIFICATION APPARATUS
App. No. 11/907,395
→
ERROR DETECTION APPARATUS THAT COMPUTES COMPENSATION VALUE BASED ON ERROR BIT POSITION AND METHOD THEREOF
App. No. 11/907,125
→
METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 11/865,242
→
FBM GENERATION DEVICE AND FBM GENERATION METHOD
App. No. 11/905,322
→
INTERFACE DEVICE AND TOPOLOGY FORMATION METHOD
App. No. 11/905,372
→
AUDIO CODING DEVICE WITH TWO-STAGE QUANTIZATION MECHANISM
App. No. 11/902,770
→
CIRCUIT DESIGN METHOD AND CIRCUIT DESIGN SYSTEM FOR CALCULATING POWER CONSUMPTION CONSIDERING IR-DROP
App. No. 11/898,916
→
COMMUNICATION TEST CIRCUIT, COMMUNICATION INTERFACE CIRCUIT, AND COMMUNICATION TEST METHOD
App. No. 11/898,658
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
App. No. 11/898,374
→
SEMICONDUCTOR DEVICE LAYOUT METHOD AND LAYOUT PROGRAM
App. No. 11/892,533
→
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE
App. No. 11/882,865
→
DEBUGGING SYSTEM, DEBUGGING CIRCUIT AND INFORMATION PROCESSING APPARATUS
App. No. 11/878,780
→
ERROR PROCESSING METHOD AND INFORMATION PROCESSING APPARATUS
App. No. 11/878,778
→
Packet cipher processor and method
App. No. 11/878,249
→
Timing analysis method and device
App. No. 11/878,264
→
PROGRAM CONTROL DEVICE AND PROGRAM CONTROL METHOD
App. No. 11/822,730
→
CONTROL METHOD AND CONTROL PROGRAM FOR PROBER
App. No. 11/812,648
→
DATA ANALYZING DEVICE AND METHOD, AND PROGRAM FOR MAKING COMPUTER EXECUTE THE DATA ANALYZING METHOD
App. No. 11/808,243
→
CONTROL SYSTEM FOR CHARGING BATTERIES AND ELECTRONIC APPARATUS USING SAME
App. No. 11/757,991
→
TIMING ANALYSIS METHOD AND TIMING ANALYSIS APPARATUS
App. No. 11/798,338
→
Communication device and communication system
App. No. 11/798,304
→
METHOD AND APPARATUS FOR SUPPORTING VERIFICATION, AND COMPUTER PRODUCT
App. No. 11/747,026
→
METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING MASTER SLICE METHOD
App. No. 11/798,165
→
CACHE MEMORY CONTROL METHOD AND CACHE MEMORY APPARATUS
App. No. 11/742,155
→
METHOD AND APPARATUS FOR SUPPORTING VERIFICATION, AND COMPUTER PRODUCT
App. No. 11/727,623
→
DELAY FAILURE TEST CIRCUIT
App. No. 11/717,769
→
PLL FREQUENCY SYNTHESIZER
App. No. 11/714,139
→
DIRECT MEMORY ACCESS CONTROLLER
App. No. 11/707,988
→
SEMICONDUCTOR DEVICE AND DATA TRANSFER METHOD
App. No. 11/706,983
→
LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER PRODUCT
App. No. 11/704,274
→
LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER PRODUCT
App. No. 11/704,273
→
APPARATUS AND METHOD OF PROCESSING INFORMATION OA A BRANCH INSTRUCTION IN A PIPELINE OPERATION
App. No. 11/699,494
→
FILE MANAGEMENT DEVICE AND ELECTRONIC EQUIPMENT
App. No. 11/651,035
→
TESTING APPARATUS AND TESTING METHOD FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
App. No. 11/647,363
→
SEMICONDUCTOR DEVICE VERIFICATION SYSTEM AND SEMICONDUCTOR DEVICE FABRICATION METHOD
App. No. 11/640,231
→
TIMING ANALYSIS METHOD AND APPARATUS, COMPUTER-READABLE PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM
App. No. 11/604,379
→
PHASE SHIFT CIRCUIT AND PHASE CORRECTING METHOD
App. No. 11/602,320
→
OFDM RECEIVER
App. No. 11/560,508
→
OFDM RECEIVER, INTERFERENCE WAVE DISCERNMENT METHOD, WINDOW CONTROL APPARATUS AND WINDOW CONTROL METHOD
App. No. 11/554,869
→
DIGITAL BROADCAST RECEPTION APPARATUS AND RECEPTION METHOD
App. No. 11/554,752
→
DEVICE AND METHOD FOR RECEIVING DIGITAL SIGNAL TRANSMITTED USING OFDM METHOD
App. No. 11/554,811
→
DIGITAL BROADCAST RECEIVER, MOBILE TERMINAL AND CHANNEL SEARCH METHOD
App. No. 11/553,144
→
RECONFIGURABLE CIRCUIT
App. No. 11/545,477
→
SOFTWARE/HARDWARE PARTITIONING PROGRAM AND METHOD
App. No. 11/538,601
→
TIMING ANALYZING METHOD AND APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 11/540,645
→
WAFER STRUCTURE WITH A PLURALITY OF FUNCTIONAL MACRO CHIPS FOR CHIP-ON-CHIP CONFIGURATION
App. No. 11/528,323
→
DESIGNING AND OPERATING OF SEMICONDUCTOR INTEGRATED CIRCUIT BY TAKING INTO ACCOUNT PROCESS VARIATION
App. No. 11/525,895
→
RECONFIGURABLE INTEGRATED CIRCUIT DEVICE TO AUTOMATICALLY CONFIGURE AN INITIALIZATION CIRCUIT
App. No. 11/524,386
→
METHOD AND APPARATUS FOR ANALYZING PERFORMANCE, AND COMPUTER PRODUCT
App. No. 11/524,398
→
Performance tuning apparatus, performance tuning method, and computer product
App. No. 11/524,384
→
METHOD AND APPARATUS FOR INSPECTING ELEMENT LAYOUT IN SEMICONDUCTOR DEVICE
App. No. 11/523,040
→
CRITICAL PATH ESTIMATING PROGRAM, ESTIMATING APPARATUS, ESTIMATING METHOD, AND INTEGRATED CIRCUIT DESIGNING PROGRAM
App. No. 11/468,900
→
FILE DELETE METHOD, FILE OPEN METHOD, STORAGE MEDIUM STORING FILE DELETE PROGRAM, AND STORAGE MEDIUM STORING FILE OPEN PROGRAM
App. No. 11/468,592
→
LAYOUT DETERMINATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, AND COMPUTER READABLE PROGRAM
App. No. 11/509,617
→
PERFORMANCE TUNING METHOD AND APPARATUS, COMPUTER-READABLE PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM
App. No. 11/506,962
→
METHOD FOR CORRECTING ELECTRON BEAM EXPOSURE DATA
App. No. 11/506,171
→
LAYOUT METHOD, CAD APPARATUS, COMPUTER-READABLE PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM
App. No. 11/504,625
→
Method and apparatus for supporting software tuning for multi-core processor, and computer product
App. No. 11/501,870
→
Processor and method for controlling a hardware break
App. No. 11/499,811
→
PROCESSOR AND METHOD FOR SELECTIVELY PROCESSING INSTRUCTION TO BE READ USING INSTRUCTION CODE ALREADY IN PIPELINE OR ALREADY STORED IN PREFECHT BUFFER
App. No. 11/497,290
→
PARALLEL PROCESSING APPARATUS DYNAMICALLY SWITCHING OVER CIRCUIT CONFIGURATION
App. No. 11/494,477
→
Reconfigurable computing device
App. No. 11/488,159
→
SECURE PROCESSOR
App. No. 11/456,437
→