PROCESSING ELEMENT AND RECONFIGURABLE CIRCUIT INCLUDING THE SAME
A processing element includes a shift register including n stages of registers mutually connected in series. Data held among the n stages of registers is rotated in synchronization with a clock signal. A number-of-stages determining circuit determines the number of stages to be used among the n stages of registers. An output terminal of the register in the last stage connects to an input terminal of the register in the first stage.
1 . A processing element comprising:
a shift register including n stages of registers mutually connected in series, and rotating held data among the n stages of registers in synchronization with a clock signal; and
a number-of-stages determining circuit determining a number of stages to be used among the n stages of registers,
wherein an output terminal of the register in a last stage connects to an input terminal of the register in a first stage.
2 . The processing element according to claim 1 , wherein the number-of-stages determining circuit includes a plurality of selectors, each of the selectors being placed between adjoining registers among the n stages of registers, each of the selectors receiving the held data output from the register in the anterior stage of the adjoining registers and the held data output from the register in the last stage, and each of the selectors selecting the held data in any of the register in the anterior stage and the register in the last stage and outputting the selected held data to the register in the posterior stage of the adjoining registers.
3 . The processing element according to claim 1 , wherein the held data includes coefficients of a spatial filter used in image processing.
4 . The processing element according to claim 1 , further comprising:
an operation unit to perform an operation on the held data output from any one of the n stages of registers in synchronization with the clock signal and input data from the outside.
5 . The processing element according to claim 4 , wherein the operation unit performs an operation on the held data output from the register in the last stage and the input data.
6 . The processing element according to claim 4 , wherein the operation unit includes a multiplier circuit to multiply the held data by the input data.
7 . The processing element according to claim 6 , wherein the operation unit includes an accumulating adder circuit to cumulatively add pieces of data output from the multiplier circuit.
8 . The processing element according to claim 1 , further comprising:
an operation unit to perform an operation on input data from the outside based on the held data output from any one of the n stages of registers in synchronization with the clock signal.
9 . The processing element according to claim 8 , wherein the operation unit performs an operation on the input data based on the held data input to the register in the last stage.
10 . The processing element according to claim 8 , wherein the operation unit includes an accumulating adder circuit in which the number of cumulative additions of the input data is controlled based on the held data.
11 . The processing element according to claim 7 , wherein output timing of data after operation is controlled based on the held data in the operation unit.
12 . The processing element according to claim 4 , further comprising:
a shift/mask circuit to perform a bit shift process and a bit mask process on the input data and output the input data to the operation unit.
13 . A reconfigurable circuit comprising:
a shift register including n stages of registers mutually connected in series, and rotating held data among the n stages of registers in synchronization with a clock signal; and
a number-of-stages determining circuit to determine a number of stages to be used among the n stages of registers,
wherein an output terminal of the register in a last stage connects to an input terminal of the register in a first stage.
14 . A processing method comprising:
providing a shift register including n stages of registers;
connecting the n stages of registers mutually in series;
rotating held data among the n stages of registers in synchronization with a clock signal;
determining a number of stages to be used among the n stages of registers, and connecting an output terminal of a register in the last stage to an input terminal of a register in the first stage.