Testing apparatus and testing method for an integrated circuit, and integrated circuit
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.
1. A testing apparatus for an integrated circuit including a plurality of shift registers, to which test patterns are inputted, configured with sequential circuit elements, said testing apparatus comprising:
a mask to specify a shift register in said plurality of shift registers which outputs an indeterminate value, based on external control signals, and to mask the indeterminate value by converting the indeterminate value, contained in the outputs from the specified shift register, setting a state value of “1”; and
an output verifier to verify the masked output results of the specified shift register, from which output results the indeterminate value is excluded;
wherein said mask comprises:
a decoder comprising a plurality of outputs as many as the number of last sequential circuits in said plurality of shift registers,
a plurality of second sequential circuits, associated one with each of said plurality outputs from the said decoder, each of said plurality of second sequential circuits has an output value determined in accordance with the associated output from said decoder, and
a plurality of logical arithmetic units, associated one with each of said plurality of second sequential circuits, each of said plurality of logical arithmetic units performing an arithmetic operation on the output value from the associated second sequential circuits and an output value from one of the last sequential circuits with the associated second sequential circuit.
2. The testing apparatus according to claim 1 , wherein said output verifier includes a compressing means for compressing the masked outputs.
3. An integrated circuit including sequential circuit elements, comprising:
a plurality of shift registers, to which test patterns are inputted, configured with said sequential circuit elements;
a mask to specify a shift register in said plurality of shift registers which outputs an indeterminate value, based on external control signals, and to mask the indeterminate value by converting the indeterminate value, contained in the outputs from the specified shift register, setting a state value of “1”; and
an output verifier to verify the masked output results of the specified shift register, from which output results the indeterminate value is excluded;
wherein said mask comprises:
a decoder comprising a plurality of outputs as many as the number of last sequential circuits in said plurality of shift registers,
a plurality of second sequential circuits, associated one with each of said plurality outputs from the said decoder, each of said plurality of second sequential circuits has an output value determined in accordance with the associated output from said decoder, and
a plurality of logical arithmetic units, associated one with each of said plurality of second sequential circuits, each of said plurality of logical arithmetic units performing an arithmetic operation on the output value from the associated second sequential circuits and an output value from one of the last sequential circuits with the associated second sequential circuit.
4. A mask circuit comprising:
a decoder comprising a plurality of outputs, a number of which corresponding to a number of last sequential circuits in a plurality of shift registers;
a plurality of sequential circuits, associated one with each of said plurality outputs and each having an output value determined in accordance with an associated output from said decoder; and
a plurality of logical arithmetic units, associated one with each of said plurality of sequential circuits and each performing an arithmetic operation on the output value from the associated sequential circuits and an output value from one of the last sequential circuits with the associated sequential circuit.