IP Library › Assignment 035507/0851
Patent Assignment
Reel/Frame 035507/0851

ASSIGNMENT OF ASSIGNOR'S INTEREST

Recorded: 2015-04-27 Received: 2015-04-27 Pages: 68
Assignor
FUJITSU SEMICONDUCTOR LIMITED
Executed: 2015-03-02
Assignee
SOCIONEXT INC.
2-10-23 SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI, KANAGAWA, JPX, 222-0033, JAPAN
Covered Applications (100)
MULTI-PORT MEMORY BASED ON DRAM CORE
App. No. 13/601,475
→
MULTI-PORT MEMORY BASED ON DRAM CORE
App. No. 13/601,406
→
MULTI-PORT MEMORY BASED ON DRAM CORE
App. No. 13/031,080
→
MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS
App. No. 12/631,240
→
MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS
App. No. 12/631,288
→
METHOD FOR DETERMINING A LENGTH OF SHIELDING OF A SEMICONDUCTOR INTEGRATED CIRCUIT WIRING
App. No. 12/071,845
→
SEMICONDUCTOR APPARATUS HAVING A LARGE-SIZE BUS CONNECTION
App. No. 11/984,932
→
TESTING APPARATUS AND TESTING METHOD FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
App. No. 11/647,363
→
MULTI-PORT MEMORY BASED ON DRAM CORE
App. No. 11/512,319
→
MEMORY SYSTEM
App. No. 11/505,838
→
MEMORY SYSTEM
App. No. 11/505,837
→
Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
App. No. 11/505,835
→
VOLTAGE GENERATOR CIRCUIT AND METHOD FOR CONTROLLING THEREOF
App. No. 11/480,904
→
TEST METHOD OF SEMICONDUCTOR DEVICES
App. No. 11/247,245
→
SEMICONDUCTOR APPARATUS HAVING A LARGE-SIZE BUS CONNECTION
App. No. 11/143,649
→
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
App. No. 10/914,163
→
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
App. No. 10/914,141
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FUNDAMENTAL CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, WIRING METHOD AND WIRING APPARATUS
App. No. 10/873,223
→
REGISTER SETTING METHOD AND SEMICONDUCTOR DEVICE
App. No. 10/772,268
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INTERFACE DEVICE AND INTERFACE DEVICE CONTROL METHOD
App. No. 10/725,587
→
SEMICONDUCTOR DEVICE HAVING INTERCONNECTION LAYER WITH MULTIPLY LAYERED SIDEWALL INSULATION FILM
App. No. 10/704,684
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING REDUCED CROSS-TALK NOISE
App. No. 10/694,997
→
MEMORY SYSTEM
App. No. 10/687,591
→
CONTACTOR APPARATUS FOR SEMICONDUCTOR DEVICES AND A TEST METHOD OF SEMICONDUCTOR DEVICES
App. No. 10/677,378
→
SEMICONDUCTOR MEMORY DEVICE
App. No. 10/671,473
→
MEMORY CIRCUIT TESTING SYSTEM, SEMICONDUCTOR DEVICE, AND MEMORY TESTING METHOD
App. No. 10/455,304
→
SEMICONDUCTOR DEVICE WITH CAPACITOR HAVING UPPER AND LOWER SHIELD LAYERS
App. No. 10/418,119
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SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
App. No. 10/404,153
→
MULTI-PORT MEMORY BASED ON DRAM CORE
App. No. 10/284,092
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SEMICONDUCTOR NONVOLATILE MEMORY FOR PERFORMING READ OPERATIONS WHILE PERFORMING WRITE OPERATIONS
App. No. 10/278,812
→
SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM
App. No. 10/227,430
→
METHOD AND APPARATUS FOR AUTOMATIC WIRING DESIGN BETWEEN BLOCK CIRCUITS OF INTEGRATED CIRCUIT
App. No. 10/209,927
→
SWITCHING CIRCUITRY
App. No. 10/158,918
→
PUSH-PULL AMPLIFIER
App. No. 10/132,168
→
SIGNAL GENERATING CIRCUIT, TIMING RECOVERY PLL, SIGNAL GENERATING SYSTEM AND SIGNAL GENERATING METHOD
App. No. 10/114,457
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 10/112,701
→
RECEIVING UNIT AND SEMICONDUCTOR DEVICE
App. No. 10/105,191
→
VIDEO DECODING DEVICE AND METHOD, AND PROGRAM PRODUCT THEREFOR
App. No. 10/105,215
→
RECEIVING UNIT, RECEIVING METHOD AND SEMICONDUCTOR DEVICE
App. No. 10/102,814
→
NONVOLATILE SEMICONDUCTOR MEMORY WITH IMPROVED SENSE AMPLIFIER OPERATING MARGIN
App. No. 10/102,660
→
RECEIVING UNIT, RECEIVING METHOD AND SEMICONDUCTOR DEVICE
App. No. 10/102,738
→
SEMICONDUCTOR MEMORY DEVICE HAVING SELF-TIMING CIRCUIT
App. No. 10/103,017
→
SEMICONDUCTOR MEMORY DEVICE IMPROVING OPERATION MARGIN AND INCREASING OPERATION SPEED REGARDLESS OF VARIATIONS IN SEMICONDUCTOR MANUFACTURING PROCESSES
App. No. 10/102,672
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SEMICONDUCTOR DEVICE PROVIDED WITH FUSE AND METHOD OF DISCONNECTING FUSE
App. No. 10/103,195
→
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH MECHANISM TO PREVENT LEAK CURRENT
App. No. 10/101,846
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HOME GATEWAY APPARATUS
App. No. 10/101,356
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SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
App. No. 10/100,075
→
APPARATUS FOR DRAWING DOTTED LINES HAVING NATURAL APPEARANCE
App. No. 10/097,374
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SEMICONDUCTOR INTEGRATED CIRCUIT WITH FUNCTION TO START AND STOP SUPPLY OF CLOCK SIGNAL
App. No. 10/097,619
→
SEMICONDUCTOR DEVICE HAVING SIMPLIFIED INTERNAL DATA TRANSFER
App. No. 10/096,425
→
MICROPROCESSOR
App. No. 10/095,568
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 10/091,507
→
CONTROL DEVICE FOR SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 10/090,826
→
SEMICONDUCTOR MEMORY
App. No. 10/085,026
→
PUSH-BUTTON SIGNAL RECEIVING CIRCUIT AND A METHOD OF DETECTING A PUSH-BUTTON SIGNAL
App. No. 10/084,152
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METHOD FOR MOUNTING ELECTRONIC PART AND PASTE MATERIAL
App. No. 10/084,370
→
CONTENT ADDRESSABLE MEMORY DEVICES DETERMINING ENTRY DATA PRIORITY BY VALID DATA LENGTH
App. No. 10/080,559
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IMAGE RECORDING APPARATUS AND SEMICONDUCTOR DEVICE
App. No. 10/080,564
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LSI LAYOUT METHOD AND APPARATUS FOR CELL ARRANGEMENT IN WHICH TIMING IS PRIORITIZED
App. No. 10/079,545
→
PACKET TRANSFER DEVICE, SEMICONDUCTOR DEVICE, AND PACKET TRANSFER SYSTEM
App. No. 10/079,405
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REGISTER SETTING METHOD AND SEMICONDUCTOR DEVICE
App. No. 10/079,891
→
A/D CONVERSION DEVICE AND A/D CONVERTER ERROR CORRECTION DEVICE
App. No. 10/078,359
→
CURRENT-VOLTAGE CONVERTER
App. No. 10/078,442
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ARITHMETIC UNIT AND RECEIVER UNIT
App. No. 10/078,368
→
OSCILLATOR CIRCUIT OF INTERNAL POWER GENERATOR CIRCUIT AND CONTROL METHOD THEREOF
App. No. 10/076,586
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SEMICONDUCTOR MEMORY HAVING A WIDE BUS-BANDWIDTH FOR INPUT/OUTPUT DATA
App. No. 10/067,236
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SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 10/066,630
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SEMICONDUCTOR MEMORY DEVICE WITH EFFICIENT AND RELIABLE REDUNDANCY PROCESSING
App. No. 10/066,603
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CONTENT ADDRESSABLE MEMORY DEVICE WITH ADVANCED PRECHARGE TIMING
App. No. 10/066,628
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POWER SUPPLY NETWORK ANALYZING METHOD, COMPUTER PROGRAM FOR EXECUTING THE METHOD, STORAGE MEDIUM AND POWER SUPPLY NETWORK ANALYZING APPARATUS
App. No. 10/062,496
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FREQUENCY MULTIPLIER
App. No. 10/062,423
→
VOLTAGE GENERATOR CIRCUIT AND METHOD FOR CONTROLLING THEREOF
App. No. 10/061,183
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FORMAL VERIFICATION METHOD
App. No. 10/060,261
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SYSTEM FOR PROGRAMMING VERIFICATION
App. No. 10/062,283
→
DATA ANALYSIS APPARATUS, DATA ANALYSIS METHOD, AND COMPUTER PRODUCTS
App. No. 10/058,792
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MEMORY SYSTEM HAVING MEMORY CONTROLLER FOR CONTROLLING DIFFERENT TYPES OF MEMORY CHIPS
App. No. 10/057,989
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X-Y ADDRESS TYPE SOLID-STATE IMAGE PICKUP DEVICE WITH AN IMAGE AVERAGING CIRCUIT DISPOSED IN THE NOISE CANCEL CIRCUIT
App. No. 10/055,901
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MULTI CHIP PACKAGE STRUCTURE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS MOUNTED IN THE SAME PACKAGE
App. No. 10/058,877
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SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A SIGNAL RECEIVING CIRCUIT
App. No. 10/050,952
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SWITCHED CAPACITOR FILTER CIRCUIT
App. No. 10/050,841
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SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SIMULTANEOUSLY READING DATA AND REFRESHING DATA
App. No. 10/046,754
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SEMICONDUCTOR INTEGRATED CIRCUIT WITH FUNCTION TO MANAGE LICENSE INFORMATION
App. No. 10/046,759
→
CONTENTS ADDRESSABLE MEMORY WITH ACCELERATED ENTRY DATA SHUNTING
App. No. 10/043,113
→
IMAGE SENSOR
App. No. 10/042,240
→
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH ENHANCED LAYOUT
App. No. 10/040,460
→
STATIC RAM WITH OPTIMIZED TIMING OF DRIVING CONTROL SIGNAL FOR SENSE AMPLIFIER
App. No. 10/038,827
→
MEMORY CONTROL SYSTEM
App. No. 10/036,539
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CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
App. No. 10/034,308
→
SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 10/032,465
→
SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 10/021,059
→
DIRECT MEMORY ACCESS CONTROLLER, AND DIRECT MEMORY ACCESS CONTROL METHOD
App. No. 10/017,321
→
METHOD OF REDUCING FLICKER NOISES OF X-Y ADDRESS TYPE SOLID-STATE IMAGE PICKUP DEVICE
App. No. 10/012,391
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SEMICONDUCTOR INTEGRATED CIRCUIT
App. No. 10/006,649
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SEMICONDUCTOR DEVICE WITH CIRCUITRY FOR EFFICIENT INFORMATION EXCHANGE
App. No. 10/006,238
→
INPUT/OUTPUT INTERFACE AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INPUT/OUTPUT INTERFACE
App. No. 10/003,048
→
METHOD AND APPARATUS FOR HIGH-SPEED READ OPERATION IN SEMICONDUCTOR MEMORY
App. No. 10/001,790
→
TESTING APPARATUS AND TESTING METHOD FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
App. No. 10/000,089
→
SEMICONDUCTOR MEMORY DEVICE
App. No. 10/000,313
→
SEMICONDUCTOR MEMORY DEVICE
App. No. 09/988,614
→
SEMICONDUCTOR MEMORY DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH A PLURALITY OF INTERNAL COUNTERS
App. No. 09/988,261
→