Semiconductor apparatus and buffer control circuit

1 . A semiconductor apparatus,

comprising:

a data processing unit for processing data;

a buffer for temporarily storing the data processed by the data processing unit;

a buffer control unit for causing the data stored in the buffer to be burst-transferred to a data storage unit;

wherein the buffer control unit allows burst-transfer of the data stored in the buffer to be started before full amount of data to be transferred in a single burst-transfer is stored in the buffer.

2 . The semiconductor apparatus as claimed in claim 1 , wherein the buffer control unit allows the burst-transfer of the data stored in the buffer to be started so as to prevent any location in the buffer in which no data to be burst-transferred has been stored from being read.

3 . The semiconductor apparatus as claimed in claim 1 , wherein the buffer control unit allows the burst-transfer of the data stored in the buffer to be started based on a determination that amount of data stored in the buffer reaches a predetermined amount value.

4 . The semiconductor apparatus as claimed in claim 3 , wherein the predetermined amount value is determined to satisfy

N >(1 −r 0 /r 1)* M,

where M being the full amount of data to be transferred in a single burst-transfer, r 0 being a rate at which data processed by the data processing unit is written to the buffer, r 1 being a rate at which data stored in the buffer is burst-transferred to the data storage unit.

5 . The semiconductor apparatus as claimed in claim 3 , further comprising:

a counter for counting amount of data stored in the buffer;

a register for storing the predetermined amount value; and

a determination circuit for determining that the amount of data counted by the counter matches the predetermined amount value stored in the register.

6 . The semiconductor apparatus as claimed in claim 3 , further comprising a deriving unit for deriving the predetermined amount value.

7 . The semiconductor apparatus as claimed in claim 5 , further comprising an output interface for outputting data to a date transfer circuit, wherein the output interface sends an output request signal to the data transfer circuit in response to an output request permission signal from the determination circuit, and causes the buffer to output data in response to an output acknowledge from the data transfer circuit.

8 . The semiconductor apparatus as claimed in claim 1 , wherein

the buffer comprises at least a first sub-buffer and a second sub-buffer;

data processed by the data processing unit is alternately stored in the first sub-buffer and the second sub-buffer by the full amount of data to be transferred in a single burst-transfer; and

the buffer control unit allows burst-transfer of the data stored in one of the sub-buffers to be started before full amount of data to be transferred in a single burst-transfer is stored in the one of the sub-buffers so as to prevent any location in the one of the sub-buffers in which no data to be burst-transferred has been stored from being read, while burst-transfer of the other of the sub-buffers is not performed.

9 . The semiconductor apparatus as claimed in claim 5 , further comprising an output interface for outputting data to a data transfer circuit, the output interface comprising a FIFO, wherein the output interface causes the buffer to output data to the FIFO in response to a read request from the determination circuit.

10 . The semiconductor apparatus as claimed in claim 1 , wherein the buffer is a double port RAM with a write port and a read port.

11 . The semiconductor apparatus as claimed in claim 1 , wherein the data processing unit is an image processing unit for processing image data.

12 . The semiconductor apparatus as claimed in claim 5 , further comprising an input interface for receiving data to be supplied to the data processing unit.

13 . The semiconductor apparatus as claimed in claim 7 , wherein the data transfer circuit comprises an arbitration circuit for arbitrating accesses to a data but to prevent conflict.

14 . The semiconductor apparatus as claimed in claim 5 , further comprising another register for storing data for enabling the function of the buffer control unit that allows burst-transfer of the data stored in the buffer to be started before full amount of data to be transferred in a single burst-transfer is stored in the buffer.

15 . A buffer control circuit for controlling a buffer that temporarily stores data processed by a data processing unit, comprising:

a counter for counting amount of data stored in the buffer;

a register for storing a predetermined amount value determined such that the buffer control circuit allows burst-transfer of data stored in the buffer to be started before full amount of data to be transferred in a single burst-transfer is stored in the buffer so as to prevent any location in the buffer in which no data to be burst-transferred has been stored from being read; and

a determination circuit for determining that the amount of data counted by the counter matches the predetermined amount value stored in the register.

16 . A method of controlling burst-transfer, the method comprising:

storing in a buffer, data to be burst-transferred;

allowing the buffer to start burst-transfer of the data stored therein before full amount of data to be transferred in a single burst-transfer is stored in the buffer, so as to prevent any location in the buffer in which no data to be burst-transferred has been stored from being read.