Granted Patent B2

US 7,512,873 · App. 11/494,477 · Granted Mar 31, 2009

Abstract

Claims (22)

1. A parallel processing apparatus dynamically switching over a circuit configuration, comprising:

a plurality of computing elements;

a network establishing connections between said plural computing elements;

a plurality of selectors provided corresponding to said plurality of computing elements within said network and controlling as to whether said computing element is connected to said network or not;

first local memories stored with data used for operations by said computing elements and data designating the operations, and connected to said respective computing elements; and

second local memories stored with data designating connections by said selectors, and connected to said respective selectors.

2. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 1 , wherein said computing element switches over the operation executed by said self computing element and one other computing element on the basis of the data stored in said first local memory.

3. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 1 , wherein said selector switches over a connection state of said self selector on the basis of the data stored in said second local memory.

4. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 1 , further comprising operation control devices connected to said plurality of computing elements and instructing each of said computing elements to switch over the operation that should be executed.

5. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 4 , wherein the switchover of the operation executed for each of said computing elements is executed based on a table stored in said operation control device and retaining information about said first computing element, said second computing element of which the operation should be switched over when the operation of said first computing element is terminated, and switchover timing thereof.

6. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 4 , wherein said operation control device includes:

a unit storing information about switchover timing at which the operation that should be executed next is set in each of said computing elements when the operation of each of said computing elements is terminated; and

a switchover unit setting, before the switchover timing, data for setting the operation that should be executed next in said computing element concerned in a disable status where the input of the data is inhibited, and making, at the switchover timing, the computing element concerned be in an enable status by canceling the disenable status where the input of the switchover data is inhibited.

7. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 1 , further comprising connection control devices connected to said plurality of selectors and instructing each of said selectors to switch over the connection.

8. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 7 , wherein the switchover of the connection for each of said selectors is executed based on a table stored in said connection control device and retaining information about said first selector, said second selector of which the connection should be switched over when the connection of said first selector is terminated, and switchover timing thereof.

9. A parallel processing apparatus dynamically switching over a circuit configuration according to claim 1 , wherein said first local memory connected to said one computing element is rewritten via said one computing element, while said second local memory connected to said one selector is rewritten via said one selector.

10. A parallel processing apparatus dynamically switching over a circuit configuration, comprising:

a plurality of computing elements;

a network establishing connections between said plural computing elements;

a plurality of selectors provided corresponding to said plurality of computing elements within said network and controlling as to whether an output from said computing element is outputted to said network or not;

third local memories stored with data used for operations by said computing elements and data designating the operations, and connected to every predetermined number of said computing elements capable of parallel processing and employed for executing a predetermined process; and

a fourth local memory stored with data designating connections by said selectors and stored with connection information about said predetermined number of computing elements.

Assignments (10)