Patent Assignment
Reel/Frame 044938/0360
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-12-21
Received: 2017-12-21
Pages: 13
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2017-12-18
Assignee
MONTEREY RESEARCH, LLC
3945 FREEDOM CIRCLE, SUITE 900, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(100)
METHODS OF REDUCING APOLIPOPROTEIN C-III
App. No. 14/757,773
→
LOAD DRIVER
App. No. 14/829,938
→
MODEL-BASED DAMAGE DETECTION TECHNIQUE FOR A STRUCTURAL SYSTEM
App. No. 14/742,330
→
Methods of Reducing Apolipoprotein C-III
App. No. 14/261,160
→
DEBUG CONTROL CIRCUIT
App. No. 14/218,169
→
SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICES
App. No. 14/204,373
→
METHODS OF REDUCING APOLIPOPROTEIN C-III
App. No. 14/173,155
→
NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 14/171,312
→
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE
App. No. 14/149,521
→
Voltage Adjustment Circuit and Display Device Driving Circuit
App. No. 14/089,048
→
LOAD DRIVER
App. No. 14/066,263
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/725,637
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 13/538,646
→
MOTOR CONTROL DEVICE WITH A CORRECTING UNIT DETERMINING A CORRECTED ROTATION ANGLE AFTER A PREDETERMINED TIME FROM A DETECTION TIME, CONTROL PROGRAM THEREFOR, AND METHOD FOR THE CONTROL
App. No. 13/371,533
→
REPLICA NODE FEEDBACK CIRCUIT FOR REGULATED POWER SUPPLY
App. No. 13/340,990
→
LOAD DRIVER
App. No. 13/100,876
→
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE
App. No. 13/071,385
→
CONTROL CIRCUIT FOR STEP-DOWN AND BOOST TYPE SWITCHING SUPPLY CIRCUIT AND METHOD FOR SWITCHING SUPPLY CIRCUIT
App. No. 13/008,374
→
OSCILLATING APPARATUS
App. No. 12/974,996
→
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
App. No. 12/860,074
→
TIMING CONTROLLER, TIMING CONTROL METHOD, AND TIMING CONTROL SYSTEM
App. No. 12/817,692
→
VOLTAGE ADJUSTMENT CIRCUIT AND DISPLAY DEVICE DRIVING CIRCUIT
App. No. 12/794,158
→
INTEGRATED CIRCUIT, DEBUGGING CIRCUIT, AND DEBUGGING COMMAND CONTROL METHOD
App. No. 12/729,864
→
NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 12/722,083
→
CHARGING CIRCUIT
App. No. 12/708,332
→
DATA CONVERSION APPARATUS, METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM FOR GENERATING CIRCUIT CONFIGURATION INFORMATION FROM CIRCUIT DESCRIPTION
App. No. 12/503,455
→
DESIGN PROGRAM, DESIGN APPARATUS, AND DESIGN METHOD FOR DYNAMIC RECONFIGURABLE CIRCUIT
App. No. 12/497,022
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 12/492,968
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 12/492,922
→
DUAL PROTOCOL INPUT DEVICE
App. No. 12/413,354
→
Self-aligned double patterning for memory and other microelectronic devices
App. No. 12/322,105
→
FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE
App. No. 12/340,274
→
SEMICONDUCTOR INTEGRATED CIRCUIT IN A CARRY COMPUTATION NETWORK HAVING A LOGIC BLOCKS WHICH ARE DYNAMICALLY RECONFIGURABLE
App. No. 12/332,673
→
SYSTEM AND METHOD FOR STACKING A PLURALITY OF ELECTRICALLY COUPLED SEMICONDUCTOR CHIPS WITH A CONDUCTIVE PIN
App. No. 12/259,100
→
MEMORY DEVICE AND METHODS FOR ITS FABRICATION
App. No. 12/199,692
→
USER INTERFACE DEVICES, METHODS, AND COMPUTER READABLE MEDIA FOR SENSING MOVEMENT OF AN ACTUATOR ACROSS A SURFACE OF A WINDOW
App. No. 12/218,021
→
COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE
App. No. 12/138,307
→
METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOTH SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES
App. No. 12/111,122
→
CIRCUIT AND METHOD FOR CASCADING PROGRAMMABLE IMPEDANCE MATCHING IN A MULTI-CHIP SYSTEM
App. No. 12/059,953
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 12/055,141
→
SIMULATION METHOD AND SIMULATION APPARATUS
App. No. 12/037,297
→
COMPUTER SYSTEM AND MEMORY SYSTEM
App. No. 12/036,634
→
SPECKLE-BASED OPTICAL NAVIGATION ON CURVED TRACKING SURFACE
App. No. 12/008,527
→
ARRAYED NEUTRON DETECTOR WITH MULTI SHIELDING ALLOWING FOR DISCRIMINATION BETWEEN RADIATION TYPES
App. No. 11/966,672
→
ACTIVE LIQUID CRYSTAL DISPLAY DRIVERS AND DUTY CYCLE OPERATION
App. No. 11/965,520
→
ALGORITHM FOR CHARGE LOSS REDUCTION AND VT DISTRIBUTION IMPROVEMENT
App. No. 11/959,122
→
REDUCED STATE QUADBIT
App. No. 11/958,557
→
DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
App. No. 11/949,521
→
FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE
App. No. 11/949,637
→
HYBRID FLASH MEMORY DEVICE
App. No. 11/873,810
→
CONTROLLED RAMP RATES FOR METAL BITLINES DURING WRITE OPERATIONS FROM HIGH VOLTAGE DRIVER FOR MEMORY APPLICATIONS
App. No. 11/872,989
→
VOLTAGE DETECTOR CIRCUIT
App. No. 11/975,097
→
CONFIGURABLE LIQUID CRYSTAL DISPLAY DRIVER SYSTEM
App. No. 11/864,137
→
CIRCUIT FOR CORRECTING SENSOR TEMPERATURE CHARACTERISTICS
App. No. 11/902,798
→
REDUCING POWER CONSUMPTION IN A LIQUID CRYSTAL DISPLAY
App. No. 11/855,281
→
POWER SUPPLY SYSTEM AND METHOD FOR CONTROLLING OUTPUT VOLTAGE
App. No. 11/898,575
→
NON-RESISTIVE LOAD DRIVER
App. No. 11/843,216
→
EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION
App. No. 11/837,949
→
READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
App. No. 11/834,420
→
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
App. No. 11/782,507
→
MULTI-SITE OPTICAL POWER CALIBRATION SYSTEM AND METHOD
App. No. 11/824,216
→
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
App. No. 11/745,327
→
TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES
App. No. 11/741,996
→
Circuit and a Method for Implementing Programmable Impedance Matching in a Multi-Chip Module
App. No. 60/909,351
→
MEMORY SYSTEM HAVING HIGH-SPEED ROW BLOCK AND COLUMN REDUNDANCY
App. No. 11/731,605
→
GLOBAL RESOURCE CONFLICT MANAGEMENT FOR AN EMBEDDED APPLICATION DESIGN
App. No. 11/707,201
→
GRAPHICAL USER ASSIGNABLE REGISTER MAP
App. No. 11/707,178
→
GLOBAL PARAMETER MANAGEMENT GRAPHICAL USER INTERFACE (GUI) FOR EMBEDDED APPLICATION DESIGN
App. No. 11/707,202
→
MEMORY DEVICE HAVING IMPLANTED OXIDE TO BLOCK ELECTRON DRIFT, AND METHOD OF MANUFACTURING THE SAME
App. No. 11/615,563
→
MEMORY SYSTEM WITH FIN FET TECHNOLOGY
App. No. 11/614,815
→
COPPER PROCESS METHODOLOGY
App. No. 11/614,770
→
METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY CELL
App. No. 11/614,050
→
METHODS FOR CONTROLLING THE PROFILE OF A TRENCH OF A SEMICONDUCTOR STRUCTURE
App. No. 11/538,403
→
CONTROL CIRCUIT OF POWER SUPPLY AND CONTROL METHOD OF THE POWER SUPPLY
App. No. 11/527,496
→
DC-DC CONVERTER CONTROL CIRCUIT, DC-DC CONVERTER, POWER SUPPLY UNIT, AND DC-DC CONVERTER CONTROL METHOD
App. No. 11/526,051
→
MEMORY ERASE MANAGEMENT SYSTEM
App. No. 11/470,958
→
ELECTRONIC DEVICE INCORPORATING SYSTEM POWER SUPPLY UNIT AND METHOD FOR SUPPLYING POWER SUPPLY VOLTAGE
App. No. 11/512,334
→
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
App. No. 11/465,701
→
PARALLEL PROCESSING APPARATUS DYNAMICALLY SWITCHING OVER CIRCUIT CONFIGURATION
App. No. 11/494,477
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 11/424,934
→
PHASE ADJUSTER CIRCUIT AND PHASE ADJUSTING METHOD
App. No. 11/447,852
→
CYCLE SIMULATION METHOD, CYCLE SIMULATOR, AND COMPUTER PRODUCT
App. No. 11/439,124
→
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
App. No. 11/438,324
→
TWO-BIT MEMORY CELL HAVING CONDUCTIVE CHARGE STORAGE SEGMENTS AND METHOD FOR FABRICATING SAME
App. No. 11/416,703
→
MEMORY DEVICE AND METHODS FOR ITS FABRICATION
App. No. 11/409,361
→
REDUCTION OF LEAKAGE CURRENT AND PROGRAM DISTURBS IN FLASH MEMORY DEVICES
App. No. 11/398,414
→
Memory system having high-speed row block and column redundancy
App. No. 60/788,214
→
INTERNALLY DERIVED ADDRESS GENERATION SYSTEM AND METHOD FOR BURST LOADING OF A SYNCHRONOUS MEMORY
App. No. 11/359,205
→
Graphical user assignable register map
App. No. 60/774,746
→
Global resource conflict management and global parameter management GUI for embedded applications
App. No. 60/774,295
→
RANDOM CACHE READ USING A DOUBLE MEMORY
App. No. 11/332,241
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 60/766,316
→
MULTI-BIT FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
App. No. 11/229,519
→
SEMICONDUCTOR MEMORY DEVICE USING READ DATA BUS FOR WRITING DATA DURING HIGH-SPEED WRITING
App. No. 11/228,777
→
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
App. No. 11/146,126
→
METHOD AND APPARATUS FOR REDUCING SOFT ERROR RATE IN SRAM ARRAYS USING ELEVATED SRAM VOLTAGE DURING PERIODS OF LOW ACTIVITY
App. No. 11/116,589
→
PROGRAMMABLE LOW VOLTAGE RESET APPARATUS FOR MULTI-VDD CHIPS
App. No. 11/075,632
→
METHODS FOR FORMING SUPER-STEEP DIFFUSION REGION PROFILES IN MOS DEVICES AND RESULTING SEMICONDUCTOR TOPOGRAPHIES
App. No. 11/069,501
→
Method of forming super-steep well profiles on MOS source/drain regions for SRAM soft error rate improvement
App. No. 60/556,961
→
Programmable low voltage induced reset scheme for multi-Vdd chips
App. No. 60/556,179
→