Replica node feedback circuit for regulated power supply

1. A power supply, comprising:

a source signal generating circuit;

an output stage;

a feedback stage;

a replica stage configured to replicate a response of the output stage to the source signal;

an output regulator coupling the replica stage to the output stage, configured to adjust a feedback signal to the source signal generating circuit by shunting the feedback stage to ground when a loaded output stage response does not match a response of the replica stage to the source signal.

2. The power supply of claim 1 , further comprising:

the output regulator comprising a plurality of current regulated transistors at least two of which share a common gate terminal.

3. The power supply of claim 2 , further comprising:

a transistor configured to shunt the feedback stage to ground.

4. The power supply of claim 3 , further comprising:

a first PFET;

a second PFET; and the first and second PFETs sharing a common gate terminal, the common gate terminal grounded via a first current sink.

5. The power supply of claim 4 , further comprising:

the second PFET driving the transistor that shunts the feedback stage; and the transistor that shunts the feedback stage regulated via a second current sink.

6. A regulator circuit, comprising:

a first transistor;

a second transistor replicating the first transistor;

an output regulator circuit coupling the first transistor to the second transistor, the regulator circuit comprising a plurality of current regulated transistors at least two of which share common gate terminal, wherein the common gate terminal grounded via a current sink.

7. The regulator circuit of claim 6 , further comprising:

the output regulator comprising a third transistor configured to shunt the second transistor to ground.

8. The regulator of claim 7 , further comprising:

a first of the at least two transistors that share a common gate terminal comprising a PFET driving the transistor that shunts the second transistor to ground; and a second of the at least two transistors that share a common gate terminal comprising a PFET grounded via a second current sink.

9. A method of generating regulated power for electronic circuits, comprising:

generating a source signal;

producing in an output stage an output power signal in response to the source signal;

replicating a response of the output stage to the source signal;

feeding a replicated response of the output stage to the source signal back to a circuit that generated the source signal; and

reducing a proportion of the source signal fed back by shunting the replicated response to ground when the output stage response to the source signal does not match the replicated response to the source signal.

10. The method of claim 9 , further comprising:

when the response of the output stage to the source signal does not match the replicated response of the output stage to the source signal, activating a plurality of current regulated transistors at least two of which share a common gate terminal.