Forming metal-semiconductor films having different thicknesses within different regions of an electronic device

1. An electronic device comprising:

a first transistor structure lying within a first region of a substrate, wherein the first transistor structure comprises a first charge storage layer, a first gate electrode overlying the first charge storage layer, and a first metal-semiconductor film overlying the first gate electrode;

a second transistor structure spaced apart from the first transistor structure and overlying a second region of the substrate, wherein the second transistor structure comprises a gate dielectric layer, a second gate electrode overlying the second gate dielectric layer, and a second metal-semiconductor film overlying the second gate electrode, wherein the first metal-semiconductor film has an averaged thickness that is significantly different than an averaged thickness of the second metal-semiconductor film; and

wherein the first transistor structure comprises a first source/drain region within the substrate underlying a portion of the first gate electrode and the second transistor structure comprises a second source/drain region within the substrate underlying a portion of the second gate electrode, wherein the first source/drain region has an average depth that is substantially the same as the second source/drain region.

2. The electronic device of claim 1 , wherein:

each of the first gate electrode and the second gate electrode includes silicon; and

the first metal-semiconductor film and the second metal-semiconductor film have substantially a same composition.

3. The electronic device of claim 1 , wherein the first transistor structure and the second transistor structure are separated from each other by a field isolation region within the substrate.

4. The electronic device of claim 3 , wherein the first region comprises a memory cell comprising a plurality of transistor structures including the first transistor structure.

5. The electronic device of claim 4 , wherein the memory cell is a non-volatile memory cell.

6. The electronic device of claim 4 , wherein the second region comprises a peripheral logic component including the second transistor structure.

7. The electronic device of claim 1 , wherein the averaged thickness of the first metal-semiconductor film has a thickness significantly less than the averaged thickness of the second metal-semiconductor film.

8. The electronic device of claim 1 , wherein the first and second metal-semiconductor films comprise a refractory metal.

9. The electronic device of claim 8 , wherein the first and second metal-semiconductor films comprise CoSi 2 .

10. The electronic device of claim 1 , wherein the first transistor structure further comprises

a third metal-semiconductor film overlying the first source/drain region.

11. The electronic device of claim 10 , wherein the third metal-semiconductor film comprises substantially a same averaged thickness as the first metal-semiconductor film.

12. The electronic device of claim 10 , wherein the second transistor structure further comprises

a fourth metal-semiconductor film overlying the second source/drain region.

13. The electronic device of claim 12 , wherein the fourth metal-semiconductor film comprises substantially a same averaged thickness as the second metal-semiconductor film.

14. The electronic device of claim 12 , wherein the third metal-semiconductor film has an averaged thickness significantly less than an averaged thickness of the fourth metal-semiconductor film.

15. The electronic device of claim 10 , wherein the first source/drain region and the second source/drain region are n-type doped regions.

16. The electronic device of claim 15 , wherein the first source/drain region and the second source/drain region comprise arsenic.

17. The electronic device of claim 1 , wherein each of the first and second gate electrodes comprises silicon.

18. The electronic device of claim 1 , wherein the first transistor structure includes an ONO stack including the first charge storage layer.

19. The electronic device of claim 1 , wherein the second transistor structure is a logic transistor.

20. An electronic device comprising:

a memory cell including a first transistor structure comprising a first charge storage layer, a first gate electrode overlying the first charge storage layer, a first metal-semiconductor film overlying the first gate electrode, a first source/drain region underlying a portion of the first gate electrode, and a second metal-semiconductor film lying within the first source/drain region;

a peripheral logic component including a second transistor structure comprising a gate dielectric layer, a second gate electrode overlying the gate dielectric layer, a third metal-semiconductor film overlying the second gate electrode, a second source/drain region underlying a portion of the second gate electrode, and a fourth metal-semiconductor film lying within the second source/drain region,

wherein:

the second transistor structure is separated from the first transistor structure by a field isolation region; and

the first and second metal-semiconductor films have an averaged thickness that is significantly different than an averaged thickness of the third and fourth metal-semiconductor film; and

the first source/drain region has an average depth that is substantially the same as the second source/drain region.