IP Library › Assignment 036050/0001
Patent Assignment
Reel/Frame 036050/0001

ASSIGNMENT OF ASSIGNOR'S INTEREST

Recorded: 2015-07-01 Received: 2015-07-01 Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications (100)
TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS
App. No. 14/789,476
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TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
App. No. 12/987,466
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SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
App. No. 12/980,716
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METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
App. No. 12/903,065
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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/898,968
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MEMORY DEVICE WITH IMPROVED DATA RETENTION
App. No. 12/898,551
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,532
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,481
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NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
App. No. 12/878,656
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SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS
App. No. 12/871,693
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SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
App. No. 12/840,165
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USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
App. No. 12/827,069
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/819,071
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 12/788,177
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SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
App. No. 12/773,232
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TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
App. No. 12/710,153
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CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
App. No. 12/650,118
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NONVOLATILE MEMORY DEVICE
App. No. 12/648,984
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CURRENT PRODUCING CIRCUIT, CURRENT PRODUCING METHOD, AND ELECTRONIC DEVICE
App. No. 12/636,386
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CONSTANT-VOLTAGE GENERATING CIRCUIT AND REGULATOR CIRCUIT
App. No. 12/619,496
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PLL CIRCUIT AND OSCILLATOR DEVICE
App. No. 12/617,234
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NON-VOLATILE SONOS-TYPE MEMORY DEVICE
App. No. 12/574,884
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METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
App. No. 12/574,079
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FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
App. No. 12/557,721
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 12/556,408
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OUTPUT CIRCUIT
App. No. 12/552,942
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MEMORY DEVICE
App. No. 12/548,034
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 12/543,035
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INTEGRATED CIRCUIT WITH CONTACT REGION AND MULTIPLE ETCH STOP INSULATION LAYER
App. No. 12/539,480
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/512,741
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/508,319
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MEMORY, MEMORY OPERATING METHOD, AND MEMORY SYSTEM
App. No. 12/502,592
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MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS
App. No. 12/494,114
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MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS
App. No. 12/494,104
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/491,970
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SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
App. No. 12/491,092
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PEAK HOLD CIRCUIT
App. No. 12/483,579
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REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY
App. No. 12/433,499
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GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
App. No. 12/424,023
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PARTIAL LOCAL SELF-BOOSTING OF A MEMORY CELL CHANNEL
App. No. 12/407,228
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PIN DIODE DEVICE AND ARCHITECTURE
App. No. 12/370,932
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METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
App. No. 12/370,950
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HIGH K STACK FOR NON-VOLATILE MEMORY
App. No. 12/351,553
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METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS
App. No. 12/346,699
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SONOS-NAND DEVICE HAVING A STORAGE REGION SEPARATED BETWEEN CELLS
App. No. 12/343,998
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HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
App. No. 12/342,011
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/341,874
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TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
App. No. 12/341,886
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HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
App. No. 12/342,008
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RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
App. No. 12/340,288
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FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE
App. No. 12/340,274
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
App. No. 12/337,461
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
App. No. 12/336,757
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ELECTRONIC CIRCUIT
App. No. 12/334,221
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METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
App. No. 12/332,146
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MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
App. No. 12/329,475
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STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
App. No. 12/327,040
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SPI ADDRESSING BEYOND 24-BITS
App. No. 12/277,911
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 12/275,121
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TEST STUCTURES FOR DEVELOPMENT OF METAL-INSULATOR-METAL (MIM) DEVICES
App. No. 12/313,089
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SIH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE
App. No. 12/290,916
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APPARATUS AND METHOD FOR PLACEMENT OF BOOSTING CELL WITH ADAPTIVE BOOSTER SCHEME
App. No. 12/262,123
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RESISTIVE MEMORY CELL ARRAY WITH COMMON PLATE
App. No. 12/290,179
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APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY
App. No. 12/255,622
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SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL STRUCTURE
App. No. 12/253,619
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SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
App. No. 12/246,981
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SYSTEM AND METHOD OF OPERATION FOR RESISTIVE CHANGE MEMORY
App. No. 12/243,836
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METHOD FOR DETECTING A VOID
App. No. 12/240,767
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SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES
App. No. 12/234,738
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QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
App. No. 12/234,740
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SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION
App. No. 12/235,321
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HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
App. No. 12/234,733
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FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
App. No. 12/234,737
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SEMICONDUCTOR DEVICE AND METHOD USING STRESS INFORMATION
App. No. 12/233,577
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3-D INTEGRATED CIRCUIT SYSTEM AND METHOD
App. No. 12/209,478
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STACKED SOLDER BALLS FOR INTEGRATED CIRCUIT DEVICE PACKAGING AND ASSEMBLY
App. No. 12/196,210
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MIRROR BIT MEMORY DEVICE APPLYING A GATE VOLTAGE ALTERNATELY TO GATE
App. No. 12/192,923
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CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING STACKED TYPE SEMICONDUCTOR DEVICES
App. No. 12/166,293
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/165,331
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MEMORY DEVICE AND METHOD
App. No. 12/134,902
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PRECISION TRENCH FORMATION THROUGH OXIDE REGION FORMATION FOR A SEMICONDUCTOR DEVICE
App. No. 12/134,087
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CONSTANT VOLTAGE CIRCUIT, CONSTANT VOLTAGE SUPPLY SYSTEM AND CONSTANT VOLTAGE SUPPLY METHOD
App. No. 12/115,934
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WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
App. No. 12/111,886
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NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE IN WHICH DRIVING ABILITY OF A SELECTOR TRANSISTOR IS VARIED
App. No. 12/058,471
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SECURE MANAGEMENT OF MEMORY REGIONS IN A MEMORY
App. No. 12/054,740
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FLIP-CHIP PACKAGE COVERED WITH TAPE
App. No. 12/012,388
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DETECTION CIRCUIT
App. No. 12/021,007
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
App. No. 11/963,400
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REDUCTION OF DEFECTS FORMED ON THE SURFACE OF A SILICON OXYNITRIDE FILM
App. No. 12/004,676
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OPERATIONAL AMPLIFIER, LINE DRIVER, AND LIQUID CRYSTAL DISPLAY DEVICE
App. No. 12/000,995
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WEAVABLE FIBER PHOTOVOLTAIC COLLECTORS
App. No. 11/947,424
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ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
App. No. 11/945,785
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SPI BANK ADDRESSING SCHEME FOR MEMORY DENSITIES ABOVE 128MB
App. No. 11/945,292
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PLL CIRCUIT
App. No. 11/987,003
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NONVOLATILE STORAGE DEVICE AND CONTROL METHOD THEREOF
App. No. 11/986,331
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METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 11/984,152
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MEMORY CELL ARRAY WITH LOW RESISTANCE COMMON SOURCE AND HIGH CURRENT DRIVABILITY
App. No. 11/985,018
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CONTROL CIRCUIT FOR SYNCHRONOUS RECTIFIER-TYPE DC-DC CONVERTER, SYNCHRONOUS RECTIFIER-TYPE DC-DC CONVERTER AND CONTROL METHOD THEREOF
App. No. 11/937,818
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SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
App. No. 11/924,169
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OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
App. No. 11/874,001
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