Method for controlling semiconductor memory device
View Patent ↗A semiconductor memory device includes a plurality of independently accessible memory cores. Each memory core includes at least one flag cell storing a flag value and a plurality of data cells storing data. An access control circuit included in the semiconductor memory device selects an access-control subject memory core from the memory cores based on the flag value of the at least one flag cell of each memory core.
1. A semiconductor memory device comprising:
a plurality of memory cores, each of which includes a plurality of non-volatile memory cells that allow a given logic value to be written, and each of which is independently accessible; and
an access control circuit selecting an access-control subject memory core from the plurality of memory cores;
wherein the plurality of non-volatile memory cells of each memory core include at least one flag cell storing a flag value and a plurality of data cells storing data, and the access control circuit selects the access-control subject memory core based on the flag value of the at least one flag cell in each memory core.
2. The semiconductor memory device according to claim 1 , wherein:
the access control circuit selects the access-control subject memory core during a write operation in an irreversible order and selects the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation;
the plurality of memory cores include a first memory core and a second memory core; and
the access control circuit writes first data to the first memory core when selected as the access-control subject memory core, sets the first memory core to be inaccessible by writing the given logic value to the flag cell of the first memory core when the access control circuit writes second data after the first data, and writes the second data to the second memory core when selected as the access-control subject memory core after the first memory core.
3. The semiconductor memory device according to claim 1 , wherein:
the at least one flag cell in each memory core includes a first flag cell and a second flag cell;
the access control circuit selects the access-control subject memory core during a write operation in an irreversible order, selects the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation, and writes a flag value indicating a data bit width to the second flag cell of the access-control subject memory core selected in the write operation when data is written to the data cells of the access-control subject memory core selected in the write operation;
the plurality of memory cores include a first memory core and a second memory core; and
the access control circuit writes first data to the first memory core when selected as the access-control subject memory core, sets the first memory core to be inaccessible by writing the given logic value to the first flag cell of the first memory core when the access control circuit writes second data after the first data, and writes the second data to the second memory core when selected as the access-control subject memory core after the first memory core.
4. The semiconductor memory device according to claim 3 , wherein:
the first data includes a plurality of bits, and the second data includes a plurality of bits, the quantity of which is the same as that of the first data; and
the access control circuit writes the second data to the first memory core when writing the second data includes only rewriting at least one of the bits of the first data to the given logic value, and the access control circuit sets the first memory core to be inaccessible and writes the second data to the second memory core when writing the second data includes rewriting at least one of the bits of the first data to a logic value inverse to the given logic value.
5. The semiconductor memory device according to claim 1 , wherein the access control circuit selects the access-control subject memory core during a write operation in an irreversible order, selects the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation, and sets the access-control subject memory core selected in the write operation to be data readable by writing the given logic value to the at least one flag cell of the access-control subject memory core selected in the write operation when writing data to the data cells of the access-control subject memory core selected in the write operation.
6. The semiconductor memory device according to claim 1 , wherein:
the access control circuit selects the access-control subject memory core during a write operation in an irreversible order, selects the access-control subject memory core during a read operation in an irreversible order that is opposite to that in the write operation;
the plurality of memory cores include a first memory core and a second memory core;
the at least one flag cell in each memory core includes a first flag cell; and
the access control circuit sets the first memory core as a data reading start position by writing the given logic value to the first flag cell of the first memory core when writing first data to the first memory core selected as the access-control subject memory core, and sets the second memory core as the data reading start position and the first memory core as a data reading end position by writing the given logic value to the first flag cell of the second memory core selected as the access-control subject memory core when writing second data to the second memory core after the first data is written.
7. The semiconductor memory device according to claim 6 , wherein
the first data includes a plurality of bits, and the second data includes a plurality of bits, the quantity of which is the same as that of the first data;
the at least one flag cell in each memory core includes the first flag cell and a second flag cell that differs from the first flag cell; and
when writing the second data includes only rewriting at least one of the bits of the first data to the given logic value, the access control circuit writes the second data to the first memory core, and when writing the second data includes rewriting at least one of the bits of the first data to a logic value inverse to the given logic value, the access control circuit sets the first memory core to be unwritable by writing the given logic value to the second flag cell of the first memory core and writes the first data to a memory core selected next in an order.
8. The semiconductor memory device according to claim 1 , wherein:
the semiconductor memory device is provided with the data and a write control value setting the flag value for each flag cell in each memory core; and
when the write control value is a first logic value, the access control circuit writes the data to the access-control subject memory core, and when the write control value is a second logic value, the access control circuit writes a value that sets the access-control subject memory core to be inaccessible to the at least one flag cell of the access-control subject memory core, sets another memory core to be accessible as the access-control subject memory core, and writes the data to the accessible access-control subject memory core.
9. A method for controlling a semiconductor memory device, wherein the semiconductor memory device includes a plurality of memory cores, each of which includes a plurality of non-volatile memory cells that allow a given logic value to be written and each of which is independently accessible and the plurality of non-volatile memory cells that form each memory core include at least one flag cell storing a flag value and a plurality of data cells storing data, the method comprising:
determining a flag value for the at least one flag cell in each memory core; and
selecting an access-control subject memory core from the plurality of memory cores based on the determination of the flag value of the at least one flag cell in each memory core.
10. The method according to claim 9 , wherein the plurality of memory cores include a first memory core and a second memory core, the method further comprising:
selecting the access-control subject memory core during a write operation in an irreversible order;
selecting the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation;
writing first data to the first memory core when selected as the access-control subject memory core;
setting the first memory core to be inaccessible by writing the given logic value to the at least one flag cell of the first memory core when writing second data after writing the first data; and
writing the second data to the second memory core when selected as the access-control subject memory core after the first memory core.
11. The method according to claim 9 , wherein the at least one flag cell include a first flag cell and a second flag cell, and the plurality of memory cores include a first memory core and a second memory core, the method further comprising:
selecting the access-control subject memory core during a write operation in an irreversible order;
selecting the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation;
writing a flag value indicating a data bit width to the second flag cell of the access-control subject memory core selected in the write operation when data is written to the data cells of the access-control subject memory core selected in the write operation;
writing first data to the first memory core when selected as the access-control subject memory core;
setting the first memory core to be inaccessible by writing the given logic value to the first flag cell of the first memory core when writing second data after the first data; and
writing the second data to the second memory core when selected as the access-control subject memory core after the first memory core.
12. The method according to claim 9 , further comprising:
selecting the access-control subject memory core during a write operation in an irreversible order;
selecting the access-control subject memory core during a read operation in an irreversible order that is the same as that in the write operation; and
setting the access-control subject memory core selected in the write operation to be data readable by writing the given logic value to the at least one flag cell of the access-control subject memory core selected in the write operation when writing data to the data cells of the access-control subject memory core selected in the write operation.
13. The method according to claim 9 , wherein the plurality of memory cores include a first memory core and a second memory core, the method further comprising:
selecting the access-control subject memory core during a write operation in an irreversible order;
selecting the access-control subject memory core during a read operation in an irreversible order that is opposite to that in the read operation;
setting the first memory core as a data reading start position by writing the given logic value to the at least one flag cell of the first memory core when writing first data to the first memory core as selected to be the access-control subject memory core; and
setting the second memory core as the data reading start position and the first memory core as a data reading end position by writing the given logic value to the at least one flag cell of the second memory core as selected to be the access-control subject memory core when writing second data to the second memory core after the first data is written.