Patent Assignment
Reel/Frame 036050/0174
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-07-02
Received: 2015-07-02
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,532
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,481
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USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
App. No. 12/827,069
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METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
App. No. 12/574,079
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/574,427
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SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
App. No. 12/543,404
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 12/543,035
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/508,319
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MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS
App. No. 12/494,104
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PIN DIODE DEVICE AND ARCHITECTURE
App. No. 12/370,932
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HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
App. No. 12/342,011
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HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
App. No. 12/342,008
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RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
App. No. 12/340,288
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
App. No. 12/336,757
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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 12/258,067
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SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL STRUCTURE
App. No. 12/253,619
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SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
App. No. 12/246,981
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METHOD FOR DETECTING A VOID
App. No. 12/240,767
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SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION
App. No. 12/235,321
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HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
App. No. 12/234,733
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PLASMA TREATED METAL SILICIDE LAYER FORMATION
App. No. 12/195,307
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SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
App. No. 12/183,756
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DC-DC CONVERTER AND CONTROL METHOD THEREOF
App. No. 12/136,579
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NONVOLATILE STORAGE DEVICE AND BIAS CONTROL METHOD THEREOF
App. No. 12/109,239
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SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME
App. No. 12/098,248
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DC-DC CONVERTER, POWER SUPPLY VOLTAGE SUPPLYING METHOD, AND POWER SUPPLY VOLTAGE SUPPLYING SYSTEM
App. No. 12/055,437
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DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES
App. No. 12/034,316
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PROGRAM AND ERASE DISABLING CONTROL OF WPCAM BY DOUBLE CONTROLS
App. No. 12/012,390
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SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING THE SAME, AND METHOD OF MANUFACTURING THE SAME
App. No. 12/004,919
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ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
App. No. 11/945,785
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METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 11/984,152
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REDUCTION OF PACKAGE HEIGHT IN A STACKED DIE CONFIGURATION
App. No. 11/983,041
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PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
App. No. 11/934,628
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OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
App. No. 11/874,001
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CONTROL CIRCUIT OF SYNCHRONOUS RECTIFICATION TYPE POWER SUPPLY UNIT, SYNCHRONOUS RECTIFICATION TYPE POWER SUPPLY UNIT AND CONTROL METHOD THEREOF
App. No. 11/902,706
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CONTROL CIRCUIT OF POWER SUPPLY UNIT WHICH CONTROLS OUTPUT POWER OF EXTERNAL POWER SUPPLY BASED UPON CURRENT FROM THE EXTERNAL POWER SUPPLY, POWER SUPPLY UNIT AND CONTROL METHOD THEREOF
App. No. 11/889,636
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METHOD OF CONSTRUCTING A STACKED-DIE SEMICONDUCTOR STRUCTURE
App. No. 11/821,653
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FAULTY DANGLING METAL ROUTE DETECTION
App. No. 11/767,620
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DUAL-BIT MEMORY DEVICE HAVING TRENCH ISOLATION MATERIAL DISPOSED NEAR BIT LINE CONTACT AREAS
App. No. 11/612,413
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PREVENTION OF OXIDATION OF CARRIER IONS TO IMPROVE MEMORY RETENTION PROPERTIES OF POLYMER MEMORY CELL
App. No. 11/608,388
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SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
App. No. 11/636,064
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METHOD OF ERASING A RESISTIVE MEMORY DEVICE
App. No. 11/633,941
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METHODS OF PROGRAMMING AND ERASING RESISTIVE MEMORY DEVICES
App. No. 11/633,800
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
App. No. 11/512,229
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FABRICATION AND METHOD OF OPERATION OF MULTI-LEVEL MEMORY CELL ON SOI SUBSTRATE
App. No. 11/493,468
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SEMICONDUCTOR DEVICE HAVING LAMINATED ELECTRONIC CONDUCTOR ON BIT LINE
App. No. 11/444,216
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DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE
App. No. 11/408,866
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SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
App. No. 11/261,176
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SEMICONDUCTOR DEVICE HAVING A DYNAMICALLY RECONFIGURABLE CIRCUIT CONFIGURATION
App. No. 11/167,310
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JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
App. No. 11/152,375
→