Granted Patent B2

US 7,911,003 · App. 11/512,229 · Granted Mar 22, 2011

Abstract

Claims (58)

1. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

a MOS transistor formed in the semiconductor substrate, the MOS transistor including a source diffusion region and a drain diffusion region;

a well formed in the semiconductor substrate;

a back gate diffusion region defined in the vicinity of the source diffusion region or the drain diffusion region, the source diffusion region, the drain diffusion region and the back gate diffusion region being of the same conductivity type having the same impurity concentration and being formed in the same well, and the back gate diffusion region being electrically connected to the source diffusion region or the drain diffusion region via wiring; and

a potential control layer, arranged in the semiconductor substrate or under the well, for controlling the potential at the semiconductor substrate or the well,

wherein the back gate diffusion region is a dummy back gate diffusion region.

2. The semiconductor integrated circuit device according to claim 1 , wherein:

the well is of a first conductivity type;

the back gate diffusion region, the source diffusion region, and the drain diffusion region are of a second conductivity type, which differs from the first conductivity type; and

the potential control layer is embedded under the well.

3. The semiconductor integrated circuit device according to claim 1 , wherein:

the semiconductor substrate is of a first conductivity type;

the well is of a second conductivity type, which differs from the first conductivity type;

the back gate diffusion region, the source diffusion region, and the drain diffusion region include a first back gate diffusion region, a first source diffusion region, and a first diffusion region, which are formed in the well and which are of the first conductivity type;

the semiconductor integrated circuit device further comprising a second back gate diffusion region, a second source diffusion region, and a second drain diffusion region, which are formed in a region adjacent to the well in the semiconductor substrate and which are of the second conductivity type, wherein the potential control layer includes:

a first potential control layer, embedded under the well, for controlling potential at the well; and

a second potential control layer, arranged in the semiconductor substrate, for controlling potential at the semiconductor substrate.

4. The semiconductor integrated circuit device according to claim 1 , wherein:

the well is one of a plurality of wells including a first well of a first conductivity type and a second well of a second conductivity type, which differs from the first conductivity type, with the first and second wells formed alternately in the semiconductor substrate; and

the back gate diffusion region, the source diffusion region and the drain diffusion region includes:

a first back gate diffusion region, a first source diffusion region, and a first drain diffusion region, which are formed in the first well and which are of the second conductivity type; and

a second back gate diffusion region, a second source diffusion region, and a second drain diffusion region, which are formed in the second well and which are of the first conductivity type;

and wherein the potential control layer is one of a plurality of potential control layers including a first potential control layer embedded under the first well and a second potential control layer embedded under the second well.

5. The semiconductor integrated circuit device according to claim 1 , wherein:

the well is one of a plurality of wells of at least two conductivity types;

the potential control layer is one of a plurality of potential control layers respectively associated with the plurality of wells; and

the potential control layers associated with the wells of the same conductivity type are electrically connected to one another in the semiconductor integrated circuit to form a network.

6. The semiconductor integrated circuit device according to claim 1 , wherein:

the well is one of a plurality of wells including a plurality of first wells of a first conductivity type and a plurality of second wells of a second conductivity type;

the potential control layer is one of a plurality of potential control layers including a plurality of first potential control layers, respectively associated with the first plurality of wells, and a plurality of second potential control layers, respectively associated with the plurality of second wells;

the plurality of first potential control layers are electrically connected to one another in the semiconductor integrated circuit device; and

the plurality of second potential control layers are electrically connected to one another in the semiconductor integrated circuit device and electrically disconnected from the plurality of first potential control layers.

7. The semiconductor integrated circuit according to claim 6 , wherein:

the plurality of first potential control layers are electrically connected to one another to form a first network in the semiconductor integrated circuit; and

the plurality of second potential control layers are electrically connected to one another to form a second network in the semiconductor integrated circuit, with the second network being electrically disconnected from the first network.

8. The semiconductor integrated circuit device according to claim 7 , wherein:

the first network applies a first controlled potential to the plurality of first potential control layers; and

the second network applies a second controlled potential to the plurality of second potential control layers.

9. The semiconductor integrated circuit according to claim 1 , wherein the MOS transistor is a field effect transistor.

10. The semiconductor integrated circuit according to claim 1 , wherein the back gate diffusion region is electrically connected to the source diffusion region or the drain diffusion region by a contact hole and wiring.

11. The semiconductor integrated circuit according to claim 1 , wherein the potential control layer is one of a plurality of potential control layers including:

a substrate potential control layer, formed in the semiconductor substrate, for controlling the potential at the semiconductor substrate; and

a well potential control layer, formed under the well, for controlling the potential at the well.

12. The semiconductor integrated circuit according to claim 1 , wherein:

the well is one of a plurality of wells including an N well and a P well; and

the potential control layer is one of a plurality of potential control layers including:

an N well potential control layer, formed under the N well, for controlling the potential of the N well; and

a P well potential control layer, formed under the P well, for controlling the potential of the P well.

13. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

a gate insulative film formed on the semiconductor substrate;

a gate electrode formed on the gate insulative film;

a well formed in the semiconductor substrate;

a source diffusion region, a drain diffusion region, and a back gate diffusion region defined in the same well, wherein the source diffusion region, the drain diffusion region, and the back gate diffusion region are of the same conductivity type having the same impurity concentration, and the back gate diffusion region is electrically connected to the source diffusion region or the drain diffusion region via wiring; and

a potential control layer, arranged under the well, for controlling the potential at the semiconductor substrate,

wherein the back gate diffusion region is a dummy back gate diffusion region.

14. The semiconductor integrated circuit according to claim 1 , wherein the back gate diffusion region and the source diffusion region are electrically short-circuited.

Assignments (9)