IP Library Granted Patent US 7,932,125
Granted Patent B2
US 7,932,125 · App. 12/183,756 · Granted Apr 26, 2011

Self-aligned charge storage region formation for semiconductor device

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Quick Facts
Patent No.
US 7,932,125
App. No.
12/183,756
Granted
Apr 26, 2011
Kind
B2
Abstract

Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Claims (31)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate;

forming a gate electrode on the layer of the nitride film stacked between the two oxide films;

removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains;

oxidizing the central portion of the nitride film; and

forming charge storage layers in the side portions of the nitride film,

wherein the charge storage layers are separated by the central portion of the nitride film.

2. The method of claim 1 , wherein the two oxide films comprise:

a tunnel oxide film formed on the semiconductor substrate; and

a top oxide film formed on the nitride film.

3. The method of claim 2 , wherein the forming the gate electrode comprises:

forming a polysilicon layer on the layer of nitride film stacked between the two oxide films;

forming a mask layer on the polysilicon layer; and

etching the polysilicon layer, the top oxide film, and the nitride film using the mask layer to form the gate electrode.

4. The method of claim 2 , wherein the forming the gate electrode comprises:

forming a polysilicon layer on the layer of nitride film stacked between the two oxide films;

forming a photoresist on the polysilicon layer; and

etching the polysilicon layer, the top oxide film, and the nitride film using the photoresist to form the gate electrode.

5. The method of claim 1 , wherein the oxidizing the central portion of the nitride film comprises oxidizing the central portion of the nitride film completely.

6. The method of claim 1 , wherein the oxidizing the central portion of the nitride film comprises oxidizing end portions of the central portion of the nitride film.

7. The method of claim 1 , wherein the removing side portions of the nitride film is performed by using an isotropic etching.

8. The method of claim 1 , wherein the oxidizing the central portion of the nitride film is performed by using a plasma oxidation.

9. The method of claim 1 , wherein the oxidizing the central portion of the nitride film is performed by using radical oxidation.

10. The method of claim 1 , wherein the forming the charge storage layers comprises:

forming the charge storage layers along the side portions of the nitride film and along side surfaces of the gate electrode; and

oxidizing the charge storage layers formed along the side surfaces of the gate electrode.

11. The method of claim 1 , wherein the forming the charge storage layers comprises:

forming the charge storage layers along the side portions of the nitride film and along side surfaces of the gate electrode; and

forming sidewall layers on side surfaces of the charge storage layers so as to cover the charge storage layers formed on the side surfaces of the gate electrode.

12. The method of claim 11 , wherein side surfaces of the charge storage layers on the side surfaces of the gate electrode are not oxidized.

13. The method of claim 1 , the method further comprising forming a source region and a drain region in the semiconductor substrate by using the gate electrode as a mask.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2008
From: INOUE, FUMIHIKO
To: SPANSION LLC
Reel/Frame 021482/0064 →