Granted Patent B2

US 7,915,663 · App. 11/493,468 · Granted Mar 29, 2011

Abstract

Claims (70)

1. A semiconductor device comprising:

an insulation layer provided on a semiconductor substrate;

two or more p-type semiconductor regions comprising a first p-type semiconductor region and other p-type semiconductor regions provided on the insulation layer;

a trench oxide film provided that surrounds each of the two or more p-type semiconductor regions to reach the insulation layer, wherein the trench oxide film isolates any two of the two or more p-type semiconductor regions from each other, and wherein the trench oxide film is a single contiguous film;

an n-type source region and an n-type drain region provided on the first p-type semiconductor region; and

a charge storage region provided above the first p-type semiconductor region between the n-type source region and the n-type drain region, wherein the charge storage region has a plurality of charge states for a memory cell.

2. The semiconductor device as claimed in claim 1 ,

wherein four or more charge states can be programmed in the charge storage region; and

wherein a voltage applying portion applies a different voltage to the first p-type semiconductor region to program a different charge state.

3. The semiconductor device as claimed in claim 2 , wherein the voltage applying portion applies a first voltage to the first p-type semiconductor region in a first period while a charge is being written into the charge storage region, and applies a second voltage, higher than the first voltage, to the first p-type semiconductor region in a second period while the charge is being written into the charge storage region after the first period.

4. The semiconductor device as claimed in claim 2 wherein the voltage applying portion applies a first voltage to the first p-type semiconductor region in a first period while a charge is being erased from the charge storage region, and applies a second voltage, lower than the first voltage, to the first p-type semiconductor region in a second period while the charge is being erased from the charge storage region after the first period.

5. The semiconductor device as claimed in claim 3 , wherein the voltage applying portion applies an identical voltage in the first period and in the second period to a source, a control gate, and a drain of the memory cell.

6. The semiconductor device as claimed in claim 1 ,

wherein the memory cell is a reference cell; and

wherein a voltage applying portion applies a different voltage to the first p-type semiconductor region to read different data from the reference cell.

7. The semiconductor device as claimed in claim 1 , wherein the trench oxide film includes an oxide silicon region or an n-type semiconductor region.

8. A semiconductor device comprising:

an insulation layer provided on a semiconductor substrate;

a first p-type semiconductor region provided on the insulation layer;

an isolation region that surrounds the first p-type semiconductor region to reach the insulation layer and that includes an oxide silicon region and an n-type semiconductor region, wherein the isolation region isolates the p-type semiconductor region from other p-type semiconductor regions, wherein the isolation region individually surrounds each of the other p-type semiconductor regions and the first p-type semiconductor region, and wherein a portion of the oxide silicon region is in contact with a plurality of individually isolated p-type semiconductor regions;

an n-type drain region provided on the first p-type semiconductor region, wherein the oxide silicon region is provided alongside the drain region;

an n-type source region provided on the first p-type semiconductor region and on the n-type semiconductor region, wherein the n-type semiconductor region is provided alongside the source region;

a charge storage region provided above the first p-type semiconductor region between the n-type source region and the n-type drain region; and

a voltage applying portion, wherein the voltage applying portion generates and communicates a different voltage to the first p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being performed.

9. The semiconductor device as claimed in claim 7 , wherein the charge storage region includes a floating gate.

10. The semiconductor device as claimed in claim 7 , wherein the charge storage region includes a trap layer of an ONO film.

11. A wireless communications device, said wireless communications device comprising:

a flash memory comprising:

an insulation layer provided on a semiconductor substrate;

two or more p-type semiconductor regions comprising a first p-type semiconductor region and other p-type semiconductor regions provided on the insulation layer;

a trench oxide film provided that surrounds each of the two or more p-type semiconductor regions to reach the insulation layer, wherein the trench oxide film isolates any two of the two or more p-type semiconductor regions from each other, and wherein the trench oxide film is a single contiguous film;

an n-type source region and an n-type drain region provided on the first p-type semiconductor region; and

a charge storage region provided above the first p-type semiconductor region between the n-type source region end the n-type drain region, wherein the charge storage region has a plurality of charge states;

a processor;

a communications component;

a transmitter;

a receiver; and

an antenna connected to the transmitter circuit and the receiver circuit.

12. The wireless communications device of claim 11 , wherein said flash memory is NAND flash memory.

13. The wireless communications device of claim 11 , wherein said flash memory is NOR flesh memory.

14. The wireless communications device of claim 11 , wherein said flash memory utilizes mirrorbits technology.

15. A computing device comprising:

a processor;

an input component;

an output component;

a memory comprising:

a volatile memory; and

a flash memory comprising:

an insulation layer provided on a semiconductor substrate;

two or more p-type semiconductor regions comprising a first p-type semiconductor region and other p-type semiconductor regions provided on the insulation layer;

a trench oxide film provided that surrounds each of the two or more p-type semiconductor regions to reach the insulation layer, wherein the trench oxide film isolates any two of the two or more p-type semiconductor regions from each other, and wherein the trench oxide film is a single contiguous film;

an n-type source region and an n-type drain region provided on the first p-type semiconductor region; and

a charge storage region provided above the first p-type semiconductor region between the n-type source region and the n-type drain region, wherein the charge storage region has a plurality of charge states.

16. The computing device of claim 15 , wherein said computing device is a personal computer (PC).

17. The computing device of claim 15 , wherein said computing device is a personal digital assistant (PDA).

18. The computing device of claim 15 , wherein said computing device is a gaming system.

19. A portable media player comprising:

a processor;

a cache;

a user input component;

a coder-decoder component; and

a memory comprising:

a flash memory comprising:

an insulation layer provided on a semiconductor substrate;

two or more p-type semiconductor regions comprising a first p-type semiconductor region and other p-type semiconductor regions provided on the insulation layer;

a trench oxide film provided that surrounds each of the two or more p-type semiconductor regions to reach the insulation layer, wherein the trench oxide film isolates any two of the two or more p-type semiconductor regions from each other, and wherein the trench oxide film is a single contiguous film;

an n-type source region and an n-type drain region provided on the first p-type semiconductor region; and

a charge storage region provided above the first p-type semiconductor region between the n-type source region and the n-type drain region, wherein the charge storage region has a plurality of charge states.

20. The portable media player of claim 19 , wherein said portable media player is a portable music player.

21. The portable media player of claim 19 , wherein said portable media player is a portable video player.

Assignments (9)