Method and apparatus for adaptive memory cell overerase compensation
View Patent ↗A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device ( 100 ) is provided for performing the adaptively compensating erase verify operation ( 500, 600 ). The memory device ( 100 ) includes at least one word line ( 402 ). One or more memory cells ( 200 ) and one or more reference cells ( 406, 408 ) are connected to the word lines ( 402 ), where the one or more reference cells ( 406, 408 ) include an erased reference cell ( 408 ) connected to each word line ( 402 ). The method ( 500, 600 ) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage ( 506, 608 ) utilizing the erased reference cell(s) ( 408 ) and verifying an erase voltage ( 514 ) of the memory cells ( 200 ) in response to the erase verify gate voltage ( 512, 614 ).
1. A semiconductor memory device comprising:
at least one word line;
one or more memory cells connected to each of the at least one word line; and
two or more reference cells connected to each of the at least one word line, the two or more reference cells comprising an erased reference cell connected to each of the at least one word line and one or more dynamic reference cells connected to each of the at least one word line, wherein the erased reference cell is located adjacent to the one or more dynamic reference cells, and wherein the erased reference cell is not one of the one or more dynamic reference cells.
2. The semiconductor memory device of claim 1 further comprising one or more bitlines connected to the at least one word line, wherein the one or more memory cells are located at the connection of the at least one word line and the one or more bitlines, and wherein the erased reference cell is connected to the at least one word line at a location wherein none of the one or more bitlines are connected thereto.
3. The semiconductor memory device of claim 1 wherein the at least one word line includes a dummy bitline portion thereof, and wherein the erased reference cell connected to the at least one word line is located within the dummy bitline portion thereof.
4. The semiconductor memory device of claim 1 further comprising a controller coupled to the at least one word line and programming the one or more memory cells connected to the at least one word line, wherein the controller cycles the erased reference cell connected to the at least one word line whenever programming any of the one or more memory cells connected to the at least one word line.
5. The semiconductor memory device of claim 4 wherein the erased reference cell has an erase-verified threshold voltage associated therewith and the one or more reference cells further include one or more dynamic reference cells connected to each of the at least one word line, and wherein the controller trims the one or more dynamic reference cells to a threshold voltage equivalent to the erase-verified threshold voltage of the erased reference cell.
6. A semiconductor memory device comprising:
at least one word line;
one or more memory cells connected to each of the at least one word line; and
one or more reference cells connected to each of the at least one word line, the one or more reference cells comprising an erased reference cell connected to each of the at least one word line, wherein an erase voltage of the one or more memory cells is verified in response to an erase verify gate voltage determined utilizing the erased reference cell, wherein the erase verify gate voltage is adaptively compensated for cycling degradation, wherein the erase voltage of the one or more memory cells is verified in a subsequent erase verify step, and wherein the erase verify step utilizes the compensated erase verify gate voltage.
7. The semiconductor memory device of claim 6 further comprising an erase verify reference cell, wherein the erase verify gate voltage is determined by biasing the erase verify reference cell at an initial erase verify gate voltage, comparing a current of the erase verify reference cell with a current of the erased reference cell and, if the current of the erase verify reference cell and the current of the erased reference cell are not equal, incrementally increasing by a predetermined voltage a gate voltage on the erased reference cell.
8. The semiconductor memory device of claim 7 wherein the current of the erase verify reference cell is compared with the current of the erased reference cell and the gate voltage on the erased reference cell is incrementally increased by the predetermined voltage until the current of the erase verify reference cell is equivalent to the current of the erased reference cell.
9. The semiconductor memory device of claim 8 wherein the erase verify reference cell is biased at the initial erase verify gate voltage and the one or more memory cells are biased at the gate voltage of the erased reference cell when the current of the erase verify reference cell is equivalent to the current of the erased reference cell to verify the erase voltage of the one or more memory cells as compared to the gate voltage of the erase verify reference cell.
10. The semiconductor memory device of claim 6 further comprising an erase verify reference cell, wherein the erase verify gate voltage is determined by biasing the erase reference cell at an initial erase verify gate voltage, comparing a current of the erased reference cell with a current of the erase verify reference cell and, if the current of the erased reference cell and the current of the erase verify reference cell are not equal, incrementally increasing by a predetermined voltage a gate voltage on the erase verify reference cell.
11. The semiconductor memory device of claim 10 wherein the current of the erased reference cell is compared with the current of the erase verify reference cell and the gate voltage on the erase verify reference cell incrementally increased by the predetermined voltage until the current of the erased reference cell is equivalent to the current of the erase verify reference cell.
12. The semiconductor memory device of claim 11 wherein the one or more memory cells are biased at the initial erase verify gate voltage and the erase verify reference cell is biased at the gate voltage of the erase verify reference cell when the current of the erased reference cell is equivalent to the current of the erase verify reference cell to verify the erase voltage of the one or more memory cells as compared to the gate voltage of the erase verify reference cell.