Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications
View Patent ↗A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
1. A system comprising:
a processor;
a bus coupled to the processor;
a non-volatile memory coupled to the bus, wherein the non-volatile memory comprises:
a semiconductor substrate;
a plurality of active regions;
a plurality of trenches separating the active regions;
a plurality of charge trapping structures disposed over the plurality of active regions, wherein the charge trapping structures are self-aligned and are separated at their respective bottom-most areas by a distance that is greater than the distance that separates respective top portions of the plurality of charge trapping structures.
2. The system of claim 1 , wherein the plurality of charge trapping structures are self-aligned by using a non-conformal oxide deposition.
3. The system of claim 1 , wherein the processor, bus, and non-volatile memory comprise an image capture device.
4. The system of claim 1 , wherein the processor, bus, and non-volatile memory comprise a communications device.
5. The system of claim 1 , wherein the processor, bus, and non-volatile memory comprise a computing device.