Patent Assignment
Reel/Frame 028840/0001
SECURITY AGREEMENT
Recorded: 2012-08-23
Received: 2012-08-23
Pages: 173
Assignors
SPANSION INC.
Executed: 2010-05-10
SPANSION LLC
Executed: 2010-05-10
SPANSION TECHNOLOGY INC.
Executed: 2010-05-10
SPANSION TECHNOLOGY LLC
Executed: 2010-05-10
Assignee
BARCLAYS BANK PLC
745 SEVENTH AVENUE, NEW YORK, NY, 10019, UNITED STATES
Covered Applications
(100)
WINDOWS IN CONDUCTIVE COVERINGS OF DIELECTRIC BODIES FOR FILTERS
App. No. 13/593,049
→
METHOD FOR ASSEMBLING AN ELECTRICAL CONNECTOR ASSEMBLY
App. No. 13/590,578
→
LOGICAL VOLUME GROUP DRIVE CONTROL
App. No. 13/562,419
→
STORAGE CAPACITOR FOR ELECTROMECHANICAL SYSTEMS AND METHODS OF FORMING THE SAME
App. No. 13/533,778
→
PROCESSING SOCIALLY NETWORKED ENTITIES
App. No. 13/436,649
→
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
App. No. 12/987,466
→
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
App. No. 12/980,716
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/905,716
→
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
App. No. 12/903,065
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/898,968
→
MEMORY DEVICE WITH IMPROVED DATA RETENTION
App. No. 12/898,551
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,532
→
METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
App. No. 12/891,310
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS
App. No. 12/891,481
→
PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
App. No. 12/887,182
→
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
App. No. 12/878,656
→
SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS
App. No. 12/871,693
→
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
App. No. 12/860,074
→
METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION
App. No. 12/850,252
→
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
App. No. 12/840,165
→
SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF
App. No. 12/837,323
→
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
App. No. 12/831,085
→
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
App. No. 12/827,069
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/819,071
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 12/788,177
→
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
App. No. 12/765,646
→
READ MODE FOR FLASH MEMORY
App. No. 12/730,452
→
ZONED ACCUMULATION CONVEYOR
App. No. 12/727,634
→
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
App. No. 12/710,153
→
MEMORY DEVICE ETCH METHODS
App. No. 12/688,477
→
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
App. No. 12/650,118
→
NONVOLATILE MEMORY DEVICE
App. No. 12/648,984
→
HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS
App. No. 12/642,162
→
SEMICONDUCTOR DEVICE
App. No. 12/624,117
→
OBJECT DETECTION DEVICE
App. No. 12/586,873
→
FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
App. No. 12/557,721
→
MEMORY DEVICE
App. No. 12/548,034
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/512,741
→
MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS
App. No. 12/494,114
→
MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS
App. No. 12/494,104
→
SORTATION CONVEYOR
App. No. 12/465,733
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF
App. No. 12/433,084
→
REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY
App. No. 12/433,499
→
GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
App. No. 12/424,023
→
PIN DIODE DEVICE AND ARCHITECTURE
App. No. 12/370,932
→
METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
App. No. 12/370,950
→
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
App. No. 12/365,010
→
SORTATION CONVEYOR APPARATUS AND METHODS
App. No. 12/356,780
→
METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS
App. No. 12/346,699
→
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
App. No. 12/342,011
→
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
App. No. 12/342,008
→
RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
App. No. 12/340,288
→
MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
App. No. 12/329,475
→
SPI ADDRESSING BEYOND 24-BITS
App. No. 12/277,911
→
SYSTEMS AND METHODS FOR ENHANCING A DATA STORE FOR HANDLING SEMANTIC INFORMATION
App. No. 12/270,616
→
SIH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE
App. No. 12/290,916
→
APPARATUS AND METHOD FOR PLACEMENT OF BOOSTING CELL WITH ADAPTIVE BOOSTER SCHEME
App. No. 12/262,123
→
APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY
App. No. 12/255,622
→
SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
App. No. 12/246,981
→
ORGANIC LIGHT EMITTING DIODE WITH ORGANIC MULTI-LAYER STRUCTURE HAVING A NON-LINEAR POTENTIAL DISTRIBUTION
App. No. 12/238,915
→
SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES
App. No. 12/234,738
→
QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
App. No. 12/234,740
→
HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
App. No. 12/234,733
→
EEPROM EMULATION IN FLASH DEVICE
App. No. 12/234,734
→
FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
App. No. 12/234,737
→
DYNAMIC ERASE STATE IN FLASH DEVICE
App. No. 12/234,736
→
3-D INTEGRATED CIRCUIT SYSTEM AND METHOD
App. No. 12/209,478
→
IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING
App. No. 12/198,381
→
CRUCIBLE HEATING APPARATUS AND DEPOSITION APPARATUS INCLUDING THE SAME
App. No. 12/196,603
→
MULTI-LEVEL STORAGE ALGORITHM TO EMPHASIZE DISTURB CONDITIONS
App. No. 12/189,746
→
OBJECT DETECTION DEVICE
App. No. 12/217,926
→
MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER
App. No. 12/141,180
→
ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE
App. No. 12/122,130
→
METHOD OF DRIVING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE IN AN INTERLACED SCANNING MODE IN WHICH A SINGLE FRAME IS DIVIDED
App. No. 12/118,901
→
MODULAR CONVEYOR TRANSFER SYSTEMS AND METHODS
App. No. 12/100,711
→
SORTATION CONVEYOR
App. No. 12/014,822
→
ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING FIRST AND SECOND CAPACITORS DISPOSED ON A SUBSTRATE WHEREIN THE FIRST CAPACITOR COMPRISES AN UNDOPED SEMICONDUCTOR LAYER ELECTRODE.
App. No. 12/013,698
→
MASK DEVICE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING THE SAME
App. No. 11/964,289
→
SORTATION SYSTEM
App. No. 11/981,752
→
ROLLER ARRANGEMENT FOR CONVEYOR
App. No. 11/853,387
→
CMOS LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL STRUCTURE, OPERATION, AND ARRAY CONFIGURATION
App. No. 11/841,468
→
CONVEYOR SYSTEMS AND METHODS
App. No. 11/888,153
→
FLAT PANEL DISPLAY INCLUDING AN OPAQUE FILM TO BLOCK AN ETERNAL LIGHT REFLECTED FROM A THIN FILM TRANSISTOR (TFT) AND A CAPACITOR
App. No. 11/773,789
→
LASER IRRADIATION DEVICE AND METHOD OF FABRICATING OLED USING THE SAME
App. No. 11/751,294
→
SORTATION CONVEYOR APPARATUS AND METHODS
App. No. 11/747,782
→
ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND DRIVING METHOD THEREOF
App. No. 11/697,802
→
LIGHT EMITTING DISPLAY DEVICE INCLUDING A DUMMY PIXEL HAVING CONTROLLED BIAS
App. No. 11/688,325
→
METHODS FOR MAKING FIXED PARALLEL PLATE MEMS CAPACITOR MICROSENSORS AND MICROSENSOR ARRAYS
App. No. 11/725,609
→
FIXED PARALLEL PLATE MEMS CAPACITOR MICROSENSOR ARRAY
App. No. 11/542,741
→
METAL-INSULATOR-METAL-INSULATOR-METAL (MIMIM) MEMORY DEVICE
App. No. 11/521,219
→
MASK FOR LITI AND LITI METHOD USING THE SAME
App. No. 11/509,574
→
MEMORY CELL CONTAINING COPOLYMER CONTAINING DIARYLACETYLENE PORTION
App. No. 11/462,525
→
RELEASABLE CONNECTION FOR SORTATION CONVEYOR PUSHER
App. No. 11/450,916
→
SORTATION CONVEYOR AND CROSSOVER SWITCH THEREFOR
App. No. 11/448,606
→
FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE
App. No. 11/432,495
→
NON-CONTACT ARTICLE ROTATING APPARATUS
App. No. 10/578,563
→
METHODS FOR FABRICATING FLASH MEMORY DEVICES
App. No. 11/412,365
→
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
App. No. 11/410,695
→
GAP-FILLING WITH UNIFORM PROPERTIES
App. No. 11/408,086
→
METHOD OF FORMING A CONTACT IN A SEMICONDUCTOR DEVICE WITH ENGINEERED PLASMA TREATMENT PROFILE OF BARRIER METAL LAYER
App. No. 11/388,976
→