Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The fist pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.
1. A method for reading data from or writing data to a memory device, comprising:
receiving a first pulse signal having a first pulse frequency at the memory device;
generating, at the memory device, a second pulse signal using the first pulse signal, the second pulse signal being a compliment of the first pulse signal and having a second pulse frequency that is equal to the first frequency;
using the first pulse signal to control first read/write operations so that first data is output from or input to the memory device at a first data rate; and
using the first and second pulse signals to control second read/write operations so that second data is output from or input to the memory device at a second data rate that is twice the first data rate.
2. The method according to claim 1 , wherein the output of the first data is triggered on select edges of a plurality of pulses of the first pulse signal.
3. The method according to claim 1 , wherein the input of the first data is triggered on select edges of a plurality of pulses of the first pulse signal.
4. The method according to claim 1 , wherein the output of the second data is triggered on select edges of a plurality of pulses of the first pulse signal and on rising edges of a plurality of pulses of the second pulse signal.
5. The method according to claim 1 , wherein the input of the second data is triggered on select edges of a plurality of pulses of the first pulse signal and on rising edges of a plurality of pulses of the second pulse signal.
6. The method according to claim 1 , further comprising setting a mode of the memory device to an operational mode in which data is output from or input to the memory device at the first data rate.
7. The method according to claim 1 , further comprising setting a mode of the memory device to an operational mode in which data is output from or input to the memory device at the second data rate.
8. The method according to claim 1 , further comprising loading address information into the memory device on select edges of a plurality of pulses of a third pulse signal received from the external device.
9. The method according to claim 8 , further comprising inhibiting at least one of the first read/write operations and the second read/write operations for a predefined period of time after the address information has been fully loaded into the memory device.
10. A memory device, comprising:
a storage device;
at least one memory controller coupled to the storage device and configured to
(a) receive a first pulse signal having a first pulse frequency from an external device,
(b) generate a second pulse signal using the first pulse signal, the second pulse signal being a compliment of the first pulse signal and having a second pulse frequency that is equal to the first frequency,
(c) control first read/write operations using the first pulse signal so that first data is output from or input to the storage device at a first data rate, and
(d) control second read/write operations using the first pulse signal and the second pulse signal so that second data is output from or input to the storage device at a second data rate that is twice the first data rate.
11. The memory device according to claim 10 , wherein the output of the first data from the storage device is triggered only on select edges of a plurality of pulses of the first pulse signal.
12. The memory device according to claim 11 , wherein the input of the first data to the storage device is triggered only on select edges of a plurality of pulses of the first pulse signal.
13. The memory device according to claim 11 , wherein the output of the second data from the storage device is triggered on select edges of a plurality of pulses of the first pulse signal and on select edges of a plurality of pulses of the second pulse signal.
14. The memory device according to claim 11 , wherein the input of the second data to the storage device is triggered on select edges of a plurality of pulses of the first pulse signal and on select edges of a plurality of pulses of the second pulse signal.
15. A memory device, comprising:
a unit cell array including a plurality of unit cells for storage of data, each unit cell configured to store one (1) bit of data;
an Input/Output buffer coupled to the unit cell array and configured to output first data read from the unit cell array to an external device and communicate second data to the unit cell array for storage therein;
at least one memory controller coupled to the Input/Output buffer and configured to
(a) receive a first pulse signal having a first pulse frequency from the external device,
(b) generate a second pulse signal using the first pulse signal, the second pulse signal being a compliment of the first pulse signal and having a second pulse frequency that is equal to the first frequency,
(c) control first read operations using the first pulse signal so that the first data is output from the Input/Output buffer at a first data rate,
(d) control first write operations using the first pulse signal so that the second data is input to the Input/Output buffer at a first data rate,
(e) control second read operations using the first pulse signal and the second pulse signal so that the first data is output from the Input/Output buffer at a second data rate that is twice the first data rate, and
(f) control second write operations using the first pulse signal and the second pulse signal so that the second data is input to the Input/Output buffer at the second data rate.
16. The memory device according to claim 15 , wherein the output of the first data from the Input/Output buffer is triggered only on select edges of a plurality of pulses of the first pulse signal.
17. The memory device according to claim 15 , wherein the input of the second data to the Input/Output buffer is triggered only on select edges of a plurality of pulses of the first pulse signal.
18. The memory device according to claim 15 , wherein the output of the second data from the Input/Output buffer is triggered on select edges of a plurality of pulses of the first pulse signal and on select edges of a plurality of pulses of the second pulse signal.
19. The memory device according to claim 15 , wherein the input of the second data to the Input/Output buffer is triggered on select edges of a plurality of pulses of the first pulse signal and on select edges of a plurality of pulses of the second pulse signal.
20. The memory device according to claim 15 , wherein the memory controller is further configured to inhibit at least one of the first read/write operations and the second read/write operations for a predefined period of time after address information has been loaded into the memory device.