Sector configure registers for a flash device generating multiple virtual ground decoding schemes
View Patent ↗Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity decoding scheme can emulate EEPROM functionality in a flash device, the combination of the conventional dual bit decoding scheme and the single program and erase entity decoding scheme can provide both dual bit high density storage and EEPROM emulation in a single flash device.
1. A flash device comprising:
one or more sector configure registers that select a decoding scheme for a first region and a second region in the flash device;
the first region comprising a plurality of single program and erase entities comprising two adjacent dual bit physical memory cells, the first region being programmed and erased to a high voltage state or a low voltage state on a basis of the single program and erase entity; and
the second region comprising a plurality of dual bit memory cells, the second region being erased to a low voltage state on a sector basis,
wherein the single program and erase entities in the first region are programmed and erased by
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
2. The flash device of claim 1 , wherein the sector configure registers store performance variable data for operating the first region on the basis of the single program and erase entity.
3. The flash device of claim 1 , wherein the single program and erase entities in the first region are programmed and erased by applying a hot-electron-injection voltage or a hot-hole-injection voltage to the first region on the basis of the single program and erase entity.
4. The flash device of claim 1 , wherein the single program and erase entities in the first region are programmed and erased by
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.
5. The flash device of claim 1 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not sequentially applied to two or more consecutive bitlines in the first region.
6. The flash device of claim 1 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not applied bitlines between the single program and erase entities.
7. A flash device comprising:
one or more sector configure registers that select a decoding scheme for a first region and a second region;
one or more first decoders that select one or more single program and erase entities in the first region for operating the first region in accordance with the single program and erase entity decoding scheme, the single program and erase entity comprising two adjacent dual bit physical memory cells;
one or more second decoders that select one or more dual bit memory cells for operating the second region in accordance with the dual bit decoding scheme,
wherein the first region is programmed and erased by
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
8. The bit flash device of claim 7 , wherein the sector configure registers store performance variable data for operating the first region on the basis of the single program and erase entity.
9. The flash device of claim 7 , wherein the sector configure registers store performance variable data for changing a voltage stage of the single program and erase entities to the high voltage state or the low voltage state on the basis of the single program and erase entity.
10. The flash device of claim 7 , wherein the first region is programmed and erased by applying a hot-electron-injection voltage or a hot-hole-injection voltage to the single program and erase entities.
11. The flash device of claim 7 , wherein the first region is programmed and erased by
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
12. The flash device of claim 7 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not sequentially applied to two or more consecutive bitlines in the first region.
13. The flash device of claim 7 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not applied bitlines between the single program and erase entities.
14. The flash device of claim 7 , wherein the first decoders comprise one or more bitline decoders that facilitate programming the first region on the basis of a single program and erase entity by changing a voltage state in the single program and erase entity to a high voltage state or a low voltage state.
15. The flash device of claim 7 , wherein the first decoders comprise one or more bitline decoders that facilitate changing a voltage state in the single program and erase entity to a high voltage state or a low voltage state and then changing the voltage state in the single program and erase entity to a voltage state opposite to the previous voltage state on the basis of the single program and erase entity.
16. A method of operating a flash device, comprising
selecting a single program and erase entity decoding scheme for a first region and a dual bit decoding scheme for a second region in the flash device;
operating the first region on a basis of a single program and erase entity, the single program and erase entity comprising two adjacent dual bit physical memory cells; and
operating the second region on a sector basis, wherein the first region is programmed and erased by
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
17. The method of claim 16 , wherein the first region and the second region are selected by one or more sector configure registers.
18. The method of claim 16 , wherein the first region of the flash device is programmed and erased on the basis of the single program and erase entity.
19. The method of claim 16 , wherein the first region is programmed and erased by applying a hot-electron-injection voltage or a hot-hole-injection voltage to the second region on the basis of the single program and erase entity.
20. The method of claim 16 , wherein the first region is programmed and erased by
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.