Flash mirror bit architecture using single program and erase entity as logical cell
View Patent ↗Flash memory systems and methods for facilitating a single logical cell erasure in a flash memory device whereby logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity.
1. A method of operating a flash device, comprising:
selecting a single program and erase entity in a sector of the flash device for erasure, the single program and erase entity comprising two adjacent dual bit physical memory cells of the flash device as a single logical cell, wherein the two adjacent dual bit physical memory cells share a common bitline, and wherein the single program and erase entity in the sector is selected for erasure without selection of other single program and erase entities in the sector for erasure being required; and
erasing the single program and erase entity.
2. The method of claim 1 , further comprising:
programming each of the two adjacent dual physical memory cells in the single program and erase entity independently from each other.
3. The method of claim 2 , wherein the programming the single program and erase entity comprises:
applying a program pulse to the single program and erase entity.
4. The method of claim 3 , wherein the programming the single program and erase entity comprises:
applying a program gate voltage to a gate,
applying a program bitline voltage to the common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and
connecting at least one of two non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.
5. The method of claim 4 , wherein the program gate voltage comprises a hot-electron-injection gate voltage and the program bitline voltage comprises a hot-electron-injection bitline voltage.
6. The method of claim 1 , wherein the erasing the single program and erase entity comprises:
applying an erase pulse to the the single program and erase entity.
7. The method of claim 1 , wherein the erasing the single program and erase entity comprises:
applying an erase gate voltage to a gate, applying an erase bitline voltage to the common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing at least one of non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
8. The method of claim 7 , wherein the erase gate voltage comprises a hot-hole-injection gate voltage and the erase bitline voltage comprises a hot-hole-injection bitline voltage.
9. The method of claim 1 , wherein the erasing the single program and erase entity further comprising:
erasing the single program and erase entity without having to perform a pre-program cycle on the single program and erase entity to place the single program and erase entity in a high voltage state prior to performing the erase cycle during the erase, wherein, for the single program and erase entity, a low voltage state is associated with an erase state and the high voltage state is associated with a program state.
10. The method of claim 1 , wherein the erasing the single program and erase entity further comprising:
erasing the single program and erase entity by performing a pre-program cycle to transition the single program and erase entity to an erase state without having to perform at least one of an erase cycle or a soft-program cycle on the single program and erase entity during the erase, wherein, for the single program and erase entity, a high voltage state is associated with the erase state and a low voltage state is associated with a program state.
11. A method of operating a flash device the method comprising:
mapping two adjacent dual bit physical memory cells in a sector of the flash device as a single program and erase entity, wherein the two adjacent dual bit physical memory cells share a common bitline;
selecting the single program and erase entity for erasure without having to select all dual bit memory cells in the sector; and
erasing the single program and erase entity without performing a sector erase to erase all dual bit memory cells in the sector.
12. The method of claim 11 , further comprising:
programming the single program and erase entity, wherein the program gate voltage comprises a hot-electron-injection gate voltage and the program bitline voltage comprises a hot-electron-injection bitline voltage.
13. The method of claim 11 , wherein the erasing the single program and erase entity comprises:
applying an erase pulse to the single program and erase entity.
14. The method of claim 11 , wherein the erasing the single program and erase entity comprises:
applying an erase gate voltage to a gate,
applying an erase bitline voltage to the common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and
allowing the non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
15. The method of claim 14 , wherein the erase gate voltage comprises a hot-hole-injection gate voltage and the erase bitline voltage comprises a hot-hole-injection bitline voltage.
16. A flash device, comprising:
a plurality of single program and erase entities each comprising two adjacent dual bit physical memory cells, wherein the two adjacent dual bit physical memory cells of a first single program and erase entity of the plurality are configured to share a common bitline, and wherein the first single program and erase entity is one of a specified number of single program and erase entities located in a sector of the flash device; and
one or more decoders, wherein a first decoder of the one or more decoders is configured to select the first single program and erase entity to facilitate erase of the first program and erase entity without selection of other single program and erase entities in the sector for erasure being required.
17. The system of claim 16 , wherein the first single program and erase entity is further configured to be erased during an erase operation without having to perform a pre-program cycle on the first single program and erase entity to place the first single program and erase entity in a high voltage state prior to performance of an erase cycle during the erase operation, wherein, for the first single program and erase entity, a low voltage state is associated with an erase state and the high voltage state is associated with a program state.
18. The system of claim 16 , wherein the first single program and erase entity is further configured to be erased by performing a pre-program cycle to transition the first single program and erase entity to an erase state without having to perform at least one of an erase cycle or a soft-program cycle on the first single program and erase entity during the erase, wherein, for the first single program and erase entity, a high voltage state is associated with the erase state and a low voltage state is associated with a program state.
19. The system of claim 16 , wherein the first single program and erase identity is further configured such that erase of the first single program and erase identity is bi-directional in that the first single program and erase identity is configurable to have an erase performed thereon in a first direction whereby the first single program and erase identity is transitionable from a high voltage state associated with a programmed state to a low voltage state associated with an erase state and configurable to have the erase performed thereon in a second direction whereby the first single program and erase identity is transitionable from a low voltage state associated with a programmed state to a high voltage state associated with an erase state.
20. The system of claim 16 , wherein the first single program and erase entity comprises sixteen or more data states.