Patent Assignment
Reel/Frame 036050/0514
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-07-02
Received: 2015-07-02
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
App. No. 12/987,466
→
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
App. No. 12/980,716
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METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
App. No. 12/903,065
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/898,968
→
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
App. No. 12/878,656
→
SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS
App. No. 12/871,693
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SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
App. No. 12/840,165
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/819,071
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 12/788,177
→
FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
App. No. 12/557,721
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 12/556,408
→
OUTPUT CIRCUIT
App. No. 12/552,942
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PEAK HOLD CIRCUIT
App. No. 12/483,579
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GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS
App. No. 12/424,023
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ELECTRONIC DEVICE, DETECTION CIRCUIT AND VOLTAGE CONTROL METHOD
App. No. 12/412,704
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METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
App. No. 12/370,950
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METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS
App. No. 12/346,699
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING
App. No. 12/341,879
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MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
App. No. 12/329,475
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 12/275,121
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TEST STUCTURES FOR DEVELOPMENT OF METAL-INSULATOR-METAL (MIM) DEVICES
App. No. 12/313,089
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APPARATUS AND METHOD FOR PLACEMENT OF BOOSTING CELL WITH ADAPTIVE BOOSTER SCHEME
App. No. 12/262,123
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/239,566
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FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
App. No. 12/234,737
→
SEMICONDUCTOR DEVICE AND METHOD USING STRESS INFORMATION
App. No. 12/233,577
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SEPERATION METHODS FOR SEMICONDUCTOR CHARGE ACCUMULATION LAYERS AND STRUCTURES THEREOF
App. No. 12/195,324
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METHOD FOR MANUFACTURING SONOS FLASH MEMORY
App. No. 12/193,266
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CONTROL CIRCUIT FOR STEP-DOWN DC-DC CONVERTER, STEP-DOWN DC-DC CONVERTER AND CONTROL METHOD THEREOF
App. No. 12/054,785
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POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER
App. No. 12/043,506
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DIODE AND RESISTIVE MEMORY DEVICE STRUCTURES
App. No. 12/072,588
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METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS
App. No. 12/031,458
→
MEMORY CELL ARRAY WITH LOW RESISTANCE COMMON SOURCE AND HIGH CURRENT DRIVABILITY
App. No. 11/985,018
→
PHOTOVOLTAIC THIN COATING FOR COLLECTOR GENERATOR
App. No. 11/873,824
→
IMPROVED ORNAND FLASH MEMORY AND METHOD FOR CONTROLLING THE SAME
App. No. 11/974,295
→
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB
App. No. 11/835,542
→
ERROR PROCESSING METHOD AND INFORMATION PROCESSING APPARATUS
App. No. 11/878,778
→
SOFTWARE DEVELOPMENT APPARATUS AND METHOD
App. No. 11/822,728
→
MULTI-STATE RESISTANCE CHANGING MEMORY WITH A WORD LINE DRIVER FOR APPLYING A SAME PROGRAM VOLTAGE TO THE WORD LINE
App. No. 11/724,773
→
DUAL-BIT MEMORY DEVICE HAVING ISOLATION MATERIAL DISPOSED UNDERNEATH A BIT LINE SHARED BY ADJACENT DUAL-BIT MEMORY CELLS
App. No. 11/616,718
→
METHOD OF PROGRAMMING, ERASING AND REPAIRING A MEMORY DEVICE
App. No. 11/633,940
→
GETTERING/STOP LAYER FOR PREVENTION OF REDUCTION OF INSULATING OXIDE IN METAL-INSULATOR-METAL DEVICE
App. No. 11/633,844
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SEMICONDUCTOR DEVICE
App. No. 11/479,379
→
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
App. No. 11/479,373
→
MEMORY SYSTEM WITH SWITCH ELEMENT
App. No. 11/419,705
→
FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE
App. No. 11/432,495
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SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONJUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES
App. No. 11/350,556
→
COMMUNICATION DATA CONTROLLER
App. No. 11/169,747
→
PROCESSING A COPOLYMER TO FORM A POLYMER MEMORY CELL
App. No. 11/068,674
→
SEMICONDUCTOR DEVICE BUILT ON PLASTIC SUBSTRATE
App. No. 10/885,959
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CIRCUIT WITH VARIATION CORRECTION FUNCTION
App. No. 10/401,604
→