Semiconductor device and method of manufacturing the same
In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
1. A semiconductor device comprising:
a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities for controlling a threshold voltage wherein the first MOS device has a characteristic that is similar to that of a depletion mode MOS device;
a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of added impurities in addition to the impurities formed on the surface of the p-type substrate for controlling a threshold voltage wherein the second MOS device has a characteristic that is similar to that of a depletion mode MOS device; and
a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively.
2. The semiconductor device according to claim 1 , wherein the first MOS device and the second MOS device are substantially equivalent in size.
3. The semiconductor device according to claim 1 , further comprising a second capacitive element connected in parallel to the first capacitive element, the second capacitive element constituted by connecting a gate layer and a diffusion layer of a first one of a pair of MOS transistors to a diffusion layer and a gate layer of a second one of the pair of MOS transistors, respectively.
4. The semiconductor device according to claim 3 , wherein the pair of MOS transistors are substantially equivalent in conduction type and size.
5. The semiconductor device according to claim 3 , wherein in the second capacitive element the pair of MOS transistors are structured such that a region of immediate-below-gate-layer is provided for each of the pair of MOS transistors, the immediate-below-gate-layer of each of the pair of MOS transistors connected to the diffusion layer of the other one of the pair of MOS transistors.
6. The semiconductor device according to claim 3 , wherein the second capacitive element is characterized by:
the regions of immediate-below-gate-layer of both of the pair of MOS transistors are biased to a predetermined voltage level; and
a capacity value of each of the pair of MOS transistors when a voltage between the diffusion layer and the gate layer is set to 0V is lower than 50% of a maximum capacity value.
7. The semiconductor device according to claim 1 , wherein the impurities added to the P-type substrate are impurities for a well layer, the well layer constituting the region of immediate-below-gate-layer of the second MOS device.
8. The semiconductor device according to claim 1 , wherein the impurities added to the P-type substrate are impurities which isolate the second MOS device from other MOS devices at the device level.
9. The semiconductor device according to claim 1 , wherein the impurities added to the P-type substrate are impurities which are added to the region of immediate-below-gate-layer for controlling a threshold voltage of the second MOS device.
10. A computing device comprising:
a processor;
an input component;
an output component;
a memory comprising:
a volatile memory; and
a non-volatile memory comprising:
a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including includes a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features; and
a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively.
11. The computing device according to claim 10 , wherein the first MOS device and the second MOS device are substantially equivalent in size.
12. The computing device according to claim 10 , further comprising a second capacitive element connected in parallel to the first capacitive element, the second capacitive element constituted by connecting a gate layer and a diffusion layer of a first one of a pair of MOS transistors to a diffusion layer and a gate layer of a second one of the pair of MOS transistors, respectively.
13. The computing device according to claim 12 , wherein the pair of MOS transistors are substantially equivalent in conduction type and size.
14. The computing device according to claim 12 , wherein in the second capacitive element the pair of MOS transistors are structured such that an region of immediate-below-gate-layer is provided for each of the pair of MOS transistors, the immediate-below-gate-layer of each of the pair of MOS transistors connected to the diffusion layer of the other one of the pair of MOS transistors.
15. The computing device according to claim 12 , wherein the second capacitive element is characterized by:
the regions of immediate-below-gate-layer of both of the pair of MOS transistors are biased to a predetermined voltage level; and
a capacity value of each of the pair of MOS transistors when a voltage between the diffusion layer and the gate layer is set to 0V is lower than 50% of a maximum capacity value.
16. The computing device according to claim 10 , wherein the impurities added to the P-type substrate are impurities for a well layer, the well layer constituting the region of immediate-below-gate-layer of the second MOS device.
17. The computing device according to claim 10 , wherein the impurities added to the P-type substrate are impurities which isolate the second MOS device from other MOS devices at the device level.
18. The computing device according to claim 10 , wherein the impurities added to the P-type substrate are impurities which are added to the region of immediate-below-gate-layer for controlling a threshold voltage of the second MOS device.
19. A wireless communications device, said wireless communications device comprising:
a non-volatile memory comprising:
a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features; and
a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively,
a processor;
a communications component;
a transmitter;
a receiver; and
an antenna connected to the transmitter circuit and the receiver circuit.
20. The device according to claim 19 , wherein the first MOS device and the second MOS device are substantially equivalent in size.
21. The device according to claim 19 , further comprising a second capacitive element connected in parallel to the first capacitive element, the second capacitive element constituted by connecting a gate layer and a diffusion layer of a first one of a pair of MOS transistors to a diffusion layer and a gate layer of a second one of the pair of MOS transistors, respectively.
22. The device according to claim 19 , wherein the second capacitive element is characterized by:
the regions of immediate-below-gate-layer of both of the pair of MOS transistors are biased to a predetermined voltage level; and
a capacity value of each of the pair of MOS transistors when a voltage between the diffusion layer and the gate layer is set to 0V is lower than 50% of a maximum capacity value.
23. A media content player comprising:
a non-volatile memory that stores one or more media content items, said non-volatile memory comprising:
a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features; and
a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively,
a user input that enables the selection of one or more of said media item;
a processor coupled to said user input and said storage component that causes the playback of a selected media item, and
one or more playback devices for conveying the playback of said media item.
24. The media content player according to claim 23 , further comprising a second capacitive element connected in parallel to the first capacitive element, the second capacitive element constituted by connecting a gate layer and a diffusion layer of a first one of a pair of MOS transistors to a diffusion layer and a gate layer of a second one of the pair of MOS transistors, respectively.
25. The media content player according to claim 24 , wherein the second capacitive element is characterized by:
the regions of immediate-below-gate-layer of both of the pair of MOS transistors are biased to a predetermined voltage level; and
a capacity value of each of the pair of MOS transistors when a voltage between the diffusion layer and the gate layer is set to 0V is lower than 50% of a maximum capacity value.
26. An image acquisition system, comprising:
an image acquisition component for acquiring image data;
a storage component for storing image data, said storage component comprising non-volatile memory comprising:
a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features; and
a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively, and
a display unit for displaying said image data stored in said storage component.
27. The image acquisition system according to claim 26 , further comprising a second capacitive element connected in parallel to the first capacitive element, the second capacitive element constituted by connecting a gate layer and a diffusion layer of a first one of a pair of MOS transistors to a diffusion layer and a gate layer of a second one of the pair of MOS transistors, respectively.
28. The image acquisition system according to claim 27 , wherein the second capacitive element is characterized by:
the regions of immediate-below-gate-layer of both of the pair of MOS transistors are biased to a predetermined voltage level; and
a capacity value of each of the pair of MOS transistors when a voltage between the diffusion layer and the gate layer is set to 0V is lower than 50% of a maximum capacity value.