Memory cell array with low resistance common source and high current drivability
View Patent ↗In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.
1. A semiconductor device comprising:
a substrate;
a first plurality of spaced-apart source regions in the substrate, the first plurality of spaced-apart source regions arranged in a first column of individual source regions;
a second plurality of spaced-apart source regions in the substrate, the second plurality of spaced-apart source regions arranged in a second column of individual source regions, wherein each source region of the first and second pluralities of spaced-apart source regions comprises only a single layer;
a first elongated conductor positioned on the substrate and connecting the first plurality of spaced-apart source regions, such that the first plurality of spaced-apart source regions form a first common source; and
a second elongated conductor positioned on the substrate and connecting the second plurality of spaced-apart source regions, such that the second plurality of spaced-apart source regions form a second common source.
2. The semiconductor device of claim 1 wherein each of the first and second conductors is of elongated, substantially straight configuration.
3. The semiconductor device of claim 2 wherein the first and second conductors are substantially parallel and in spaced relation.
4. The semiconductor device of claim 3 and further comprising an isolation region between the first plurality of source regions and the second plurality of source regions.
5. The semiconductor device of claim 3 and further comprising a resistive memory device over the substrate and positioned between the first plurality of source regions and the second plurality of source regions.
6. The semiconductor device of claim 1 and further comprising a conductive element on the substrate and on which the resistive memory device is positioned.
7. The semiconductor device of claim 6 and further comprising a drain region in the substrate, and wherein the conductive element is in contact with the drain region.
8. The semiconductor device of claim 7 wherein the conductive element comprises a conductive plug.
9. The semiconductor device of claim 7 wherein the conductive element comprises a pedestal which includes a first portion in contact with the drain region, and a second portion connected to the first portion and spaced from the substrate, the second portion being wider in cross-sectional width than the first portion.
10. The semiconductor device of claim 9 wherein the first portion is narrower in cross-sectional width than the cross-sectional width of the drain region.
11. The semiconductor device of claim 10 wherein the conductive element is generally T-shaped in cross-section.
12. The semiconductor device of claim 11 wherein the conductive element is metal.