Semiconductor memory comprising dual charge storage nodes and methods for its fabrication
View Patent ↗A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
1. A semiconductor memory device comprising:
a semiconductor substrate having a surface;
a dielectric plug having a first portion extending below the surface and a second portion extending above the surface wherein the second portion has a first side, a second side, and a top;
a layer of semiconductor material extending over the first side, the second side and the top of the dielectric plug;
a first storage node formed on the layer of semiconductor material extending over the first side, and a second storage node formed on the layer of semiconductor material extending over the second side;
a gate dielectric overlying the layer of semiconductor material extending over the top; and
a control gate overlying the first storage node, the second storage node, and the gate dielectric.
2. The semiconductor device of claim 1 comprising a layer of gate insulating material overlying the layer of semiconductor material.
3. The semiconductor memory device of claim 1 comprising:
a layer of tunnel oxide overlying the layer of semiconductor material;
a layer of charge storage material overlying the layer of tunnel oxide; and
a second dielectric layer overlying the charge storage material.
4. The semiconductor device of claim 1 wherein the charge storage material comprises a layer of silicon rich nitride.
5. The semiconductor device of claim 1 comprising:
a trench extending into the semiconductor substrate; and
a dielectric fill material filling the trench.
6. The semiconductor device of claim 1 wherein the layer of semiconductor material comprises a layer of monocrystalline semiconductor material.