Ornand flash memory and method for controlling the same
View Patent ↗A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.
1. A semiconductor device comprising:
a memory cell array comprising a plurality of non-volatile memory cells;
a read circuit that transfers the data from the memory cell array;
a storage unit that stores data transferred from the memory cell array; and
a control circuit that selects between:
a primary reading mode configured to store the data transferred from the memory cell array into the first storage unit and to output the data; and
a secondary reading mode configured to store a plurality of pieces of divisional data in the first storage unit, the plurality of pieces of divisional data being formed by dividing the data transferred from the memory cell array and outputting the divisional data.
2. The semiconductor device as claimed in claim 1 , wherein, in the secondary reading mode, while the first storage unit outputs a first divisional data of the plurality of pieces of divisional data, a second divisional data that comprises the next piece of divisional data among the plurality of pieces of divisional data is transferred from the memory cell array and stored in the first storage unit.
3. The semiconductor device as claimed in claim 2 , wherein a time required for transferring the first divisional data from the memory cell array to the first storage unit is shorter than a time required for transferring the second divisional data from the memory cell array to the first storage unit.
4. The semiconductor device as claimed in claim 1 , wherein a time required for transferring the divisional data from the memory cell array to the first storage unit in the secondary reading mode is shorter than a time required for transferring the area data from the memory cell array to the first storage unit in the primary reading mode.
5. The semiconductor device as claimed in claim 1 , further comprising:
a high-voltage generating circuit that generates voltages to be applied to the memory cell array when the data is read from the memory cell array,
wherein the high-voltage generating circuit generates a higher voltage in the secondary reading mode than in the primary reading mode.
6. The semiconductor device as claimed in claim 1 ,
wherein the read circuit reads the data from the memory cell array with a higher rate of power consumption in the secondary reading mode than in the primary reading mode.
7. The semiconductor device as claimed in claim 1 , further comprising:
a bit line coupled to a memory cell from which the data is read out; and
a transistor that controls a current to be supplied to the bit line when the data is read from the memory cell,
wherein the transistor supplies a higher current to the bit line in the secondary reading mode than in the primary reading mode.
8. The semiconductor device as claimed in claim 1 , further comprising:
a bit line coupled to a memory cell from which the data is read out; and
a first comparator circuit configured to compare a voltage of the bit line with a reference voltage,
wherein a current source transistor provided for the first comparator circuit supplies a higher current to the first comparator circuit in the secondary reading mode than in the primary reading mode.
9. The semiconductor device as claimed in claim 1 , further comprising:
a second comparator circuit configured to compare a signal representing a current flowing through a memory cell from which the data is read out with a signal representing a current flowing through a reference cell,
wherein a current source transistor provided for the second comparator circuit supplies a higher current to the second comparator circuit in the secondary reading mode than in the primary reading mode.
10. The semiconductor device as claimed in claim 1 , further comprising:
a second storage unit configured to hold the area data stored in the first storage unit, and later outputs the area data to the outside.
11. The semiconductor device as claimed in claim 10 , further comprising:
a switch configured to transfer the area data from the first storage unit to the second storage unit in the primary reading mode, and output the divisional data from the first storage unit to the outside without the use of the second storage unit and transfers the area data to the second storage unit in the secondary reading mode.
12. The semiconductor device as claimed in claim 10 , wherein:
the semiconductor device is configured to perform a copy back operation to write the area data into another area, after storing the area data in the second storage unit;
the area includes a spare area configured to store spare data that contains flag data indicating validity of the area data; and
the control circuit is configured to output a part of the spare data containing the flag data to the outside.
13. The semiconductor device as claimed in claim 1 , wherein:
the semiconductor device is configured to perform a copy back operation to write the area data into another area, after storing the area data in the first storage unit;
the area includes a spare area configured to store spare data that contains flag data indicating validity of the area data; and
the control circuit is configured to output a part of the spare data containing the flag data to the outside.
14. A method of controlling a semiconductor device that has a memory cell array including non-volatile memory cells, a read circuit that transfers data from the memory cell array, an area comprised in the memory cell array and stores area data, and a first storage unit that holds data transferred from the memory cell array and later outputs the data to an outside, the method comprising:
a primary reading operation that includes storing the area data transferred from the memory cell array by the read circuit into the first storage unit, and outputting the area data from the first storage unit to the outside;
a secondary reading operation that includes storing a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array into the first storage unit, and outputting the divisional data from the first storage unit to the outside; and
selecting between a primary reading mode and a secondary reading mode.
15. The method as claimed in claim 14 , wherein:
storing the plurality of pieces of divisional data includes:
outputting first divisional data from the first storage unit to the outside, the first divisional data being one of the plurality of pieces of divisional data; and
storing second divisional data transferred from the memory cell array into the first storage unit, the second divisional data being the next one of the plurality of pieces of divisional data;
wherein storing the second divisional data is carried out while outputting the first divisional data is being carried out.
16. The method as claimed in claim 14 , further comprising:
a copy back operation that includes storing the area data into the first storage unit and writing the area data into another area,
wherein the region includes a spare area that stores spare data that contains flag data indicating validity of the area data; and
the copy back operation includes outputting first divisional spare data that is one of the plurality of pieces of divisional data formed by dividing the spare data from the first storage unit to the outside, and storing second divisional spare data that is the next one of the plurality of pieces of divisional data into the first storage unit, the second divisional spare data being transferred from the memory cell array; and
storing the second divisional spare data is carried out while outputting the first divisional spare data is being carried out.
17. A system, comprising:
a processor;
a cache;
a user input component; and
a flash memory having at least one memory cell, the memory cell comprising:
nonvolatile memory;
a read circuit that transfers data from the memory cell;
an area in the memory cell array that stores area data;
one or more storage units with output to an outside; and
a control circuit that selects between varying modes of data.
18. The system as recited in claim 17 wherein the system is a portable media player.
19. The system as recited in claim 17 wherein the system is a cellular telephone.
20. The system as recited in claim 17 wherein the system is a computing device.
21. A system, comprising:
a processor;
a cache;
a user input component; and
a flash memory having a memory cell array, the memory cell array comprising a plurality of nonvolatile memory cells;
a read circuit that transfers the data from the memory cell array;
one or more storage units that stores area data transferred from the memory cell array; with output to an outside; and
a control circuit that selects between:
a primary reading mode configured to store the data transferred from the memory cell array into the first storage unit and to output the data; and
a secondary reading mode configured to store a plurality of pieces of divisional data in the first storage unit, the plurality of pieces of divisional data being formed by dividing the data transferred from the memory cell array and outputting the divisional data.
22. The system as recited in claim 17 wherein the system is a portable media player.
23. The system as recited in claim 17 wherein the system is a cellular telephone.
24. The system as recited in claim 17 wherein the system is a computing device.