Memory system with switch element
A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.
1. A method for manufacturing a memory system comprising:
forming a switch element with resistive change having a first side and a second side;
forming a cell transistor having a gate terminal, the cell transistor is a junction field effect transistor;
forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, the memory cell is a resistive change memory cell;
connecting a word line and the memory cell at the first side, including connecting a voltage source to the word line, the voltage source provides a negative voltage value;
connecting a bit line and the memory cell, the bit line provides a current path; and
connecting a reference source only to a source of the memory cell, the reference source is a reference voltage.
2. The method as claimed in claim 1 further comprising connecting a sense circuit and the bit line.
3. The method as claimed in claim 1 wherein connecting the bit line and the memory cell includes:
connecting a select transistor between the memory cell and the bit line; and
connecting a block select to a select gate of the select transistor.
4. The method as claimed in claim 1 wherein connecting the reference source and the memory cell includes:
connecting a select transistor between the memory cell and the reference source; and
connecting a block select to a select gate of the select transistor.
5. The method as claimed in claim 1 wherein forming the cell transistor is the junction field effect transistor or a Schotty gate field effect transistor.
6. The method as claimed in claim 1 further comprising setting the switch element to a state comprises:
turning the switch element to an “on” state with a high voltage V 1 and a low current I 1 ; and
turning the switch element to an “off” state with a low voltage V 2 and a high current I 2 .
7. The method as claimed in claim 1 further comprising programming the memory cell comprises:
connecting a voltage source to the word line, the voltage source provides a voltage value V 1 ; and
connecting a sense circuit and the bit line, the sense circuit is turned “on” with current value of I 1 .
8. The method as claimed in claim 1 further comprising erasing the memory cell comprises:
connecting a voltage source to the word line, the voltage source provides a voltage value V 2 ; and
connecting a sense circuit and the bit line, the sense circuit is turned “on” with current value of I 2 .
9. A memory system comprising:
a switch element with resistive change having a first side and a second side;
a cell transistor having a gate terminal is a junction field effect transistor;
a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side is a resistive change memory cell;
a voltage source connected to a word line connected with the memory cell at the first side, the voltage source provides a negative voltage value;
a bit line connected with the memory cell provides a current path; and
a reference source connected with only a source of the memory cell is a reference voltage.
10. The system as claimed in claim 9 further comprising a sense circuit connected with the bit line.
11. The system as claimed in claim 9 wherein the bit line connected with the memory cell includes:
a select transistor between the memory cell and the bit line; and
a block select connected to a select gate of the select transistor.
12. The system as claimed in claim 9 wherein the reference source connected with the memory cell includes:
a select transistor between the memory cell and the reference source; and
a block select connected to a select gate of the select transistor.
13. The system as claimed in claim 9 wherein the cell transistor is the junction field effect transistor or a Schotty gate field effect transistor.
14. The system as claimed in claim 9 wherein the switch element is responsive to:
an “on” state with the word line provided a high voltage V 1 and a low current I 1 ; and
an “off” state with the word line provided a low voltage V 2 and a high current I 2 .
15. The system as claimed in claim 9 wherein the memory cell is programmed by:
a voltage source connected to the word line, the voltage source provides a voltage value V 1 ; and
a sense circuit connected with the bit line, the sense circuit is turned “on” with current value of I 1 .
16. The system as claimed in claim 9 wherein the memory cell is erased by:
a voltage source connected to the word line, the voltage source provides a voltage value V 2 ; and
a sense circuit connected with the bit line, the sense circuit is turned “on” with current value of I 2 .
17. A method for manufacturing a memory system comprising:
forming a metal-insulator-metal element having a first side and a second side;
forming a junction field effect transistor having a gate terminal, a source terminal, and a drain terminal;
forming a memory cell, having the metal-insulator-metal element and the junction field effect transistor, with the gate terminal connected to the second side;
connecting a word line and the memory cell at the first side, including connecting a voltage source to the word line, the voltage source provides a negative voltage value;
connecting a bit line and the memory cell with the junction field effect transistor, wherein the junction field effect transistor has a first block select connected to the gate terminal, the source terminal connected to the memory cell, and the drain terminal connected to the bit line;
connecting a ground only to the source terminal of the junction field effect transistor of the memory cell wherein the junction field effect transistor has a second block select connected to the gate terminal, the source terminal connected to the ground, and the drain terminal connected to the memory cell; and
connecting a sense circuit and the bit line.
18. The method as claimed in claim 17 further comprising programming the memory cell comprises:
connecting a voltage source to the word line, the voltage source provides a voltage value V 1 ;
connecting the voltage source to the first block select, the voltage source provides a ground potential;
connecting the voltage source to the second block select, the voltage source provides a negative voltage value; and
turning the sense circuit “on” with current value of I 1 .
19. The method as claimed in claim 17 further comprising erasing the memory cell comprises:
connecting a voltage source to the word line, the voltage source provides a voltage value V 2 ;
connecting the voltage source to the first block select, the voltage source provides a ground potential;
connecting the voltage source to the second block select, the voltage source provides a negative voltage value; and
turning the sense circuit “on” with current value of I 2 .
20. The method as claimed in claim 17 further comprising reading the memory cell comprises:
connecting a voltage source to the word line, the voltage source provides a negative voltage value;
connecting the voltage source to the first block select and the second block select, the voltage source provides a ground potential; and
turning the sense circuit “on”.
21. The method as claimed in claim 17 further comprising protecting the memory cell comprises turning the sense circuit “off”.
22. A memory system comprising:
a metal-insulator-metal element having a first side and a second side;
a junction field effect transistor having a gate terminal, a source terminal, and a drain terminal;
a memory cell, having the metal-insulator-metal element and the junction field effect transistor, with the gate terminal connected to the second side;
a word line connected to the memory cell at the first side, a voltage source connected to the word line, the voltage source provides a negative voltage value;
a bit line connected to the memory cell with the junction field effect transistor, wherein the junction field effect transistor has a first block select connected to the gate terminal, the source terminal connected to the memory cell, and the drain terminal connected to the bit line;
a ground only to the source terminal of the junction field effect transistor of the memory cell wherein the junction field effect transistor has a second block select connected to the gate terminal, the source terminal connected to the ground, and the drain terminal connected to the memory cell; and
a sense circuit connected to the bit line.
23. The system as claimed in claim 22 wherein the memory cell is programmed by:
a voltage source connected to the word line, the voltage source provides a voltage value V 1 ;
the voltage source connected to the first block select, the voltage source provides a ground potential;
the voltage source connected to the second block select, the voltage source provides a negative voltage value; and
the sense circuit turned “on” with current value of I 1 .
24. The system as claimed in claim 22 further comprising the memory cell is erased by:
a voltage source connected to the word line, the voltage source provides a voltage value V 2 ;
the voltage source connected to the first block select, the voltage source provides a ground potential;
the voltage source connected to the second block select, the voltage source provides a negative voltage value; and
the sense circuit turned “on” with current value of I 2 .
25. The system as claimed in claim 22 further comprising the memory cell is read by:
a voltage source connected to the word line, the voltage source provides a negative voltage value;
the voltage source connected to the first block select and the second block select, the voltage source provides a ground potential; and
the sense circuit turned “on”.
26. The system as claimed in claim 22 further comprising the memory cell is protected by the sense circuit turned “off”.