Semiconductor device and control method of the same
View Patent ↗The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit ( 16 ) connected to a core cell ( 12 ) provided in a nonvolatile memory cell array ( 10 ), a second current-voltage conversion circuit ( 26 ) connected to a reference cell ( 22 ) through a reference cell data line ( 24 ), a sense amplifier ( 18 ) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit ( 28 ) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit ( 30 ) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
1. A computing device comprising:
a processor;
an input component;
an output component;
a memory comprising:
a volatile memory; and
a flash memory comprising:
a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array;
a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, wherein the second current-voltage conversion circuit has an average circuit averaging outputs from multiple reference cells, and the second current-voltage conversion circuit outputs an output from the average circuit;
a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit;
a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level; and
a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line.
2. The computing device of claim 1 , wherein said computing device is a personal computer (PC).
3. The computing device of claim 1 , wherein said computing device is a personal digital assistant (PDA).
4. The computing device of claim 1 , wherein said computing device is a gaming system.
5. The flash memory of claim 1 , wherein:
the second current-voltage conversion circuit has a differential circuit to which the voltage level at the reference cell data line and the predefined voltage level are input;
the compare circuit has a first FET having a gate connected to an output from the differential circuit and a source and drain connected to a voltage source and an output node and a second FET having a gate connected to a gate of a current source FET in the differential circuit and a source and a drain connected to the output node and a ground level; and
an output of the compare circuit is connected to the output node.
6. The flash memory of claim 1 , wherein the average circuit has a first average circuit outputting to the first current-voltage conversion circuit, and a second average circuit outputting an output thereof to the sense amplifier.