High read speed electronic memory with serial array transistors
View Patent ↗Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.
1. Electronic memory, comprising:
a plurality of memory transistors electrically coupled in a serial array, with one end of the array coupled to a metal bitline of the electronic memory;
a pass transistor having a gate that is coupled to the serial array and having a drain or source coupled to an electrical contact off of a second metal bitline of the electronic memory; and
a sensing circuit that measures current through the second metal bitline or voltage of the second metal bitline to determine a state of one of the plurality of memory transistors.
2. The electronic memory of claim 1 , the sensing circuit measures the current through the second metal bitline or the voltage of the second metal bitline as modulated by a potential at the gate of the pass transistor.
3. The electronic memory of claim 1 , the pass transistor has small resistance relative to the plurality of memory transistors.
4. The electronic memory of claim 1 , the pass transistor has small capacitance relative to the metal bitline and second metal bitline.
5. The electronic memory of claim 1 , further comprising:
a second plurality of memory transistors electrically coupled in a second serial array, with one end of the second array coupled to the second metal bitline; and
a second pass transistor having a gate that is coupled to the second array and having a drain and source that couple an electrical contact off of the metal bitline of the electronic memory to ground.
6. The electronic memory of claim 5 , further comprising a second sensing circuit that measures current through the metal bitline or voltage of the metal bitline in order to determine a state of one of the second plurality of memory transistors.
7. The electronic memory of claim 1 , further comprising a processing circuit that induces or applies a pre-charge voltage to the serial array to charge the gate of the pass transistor for determining the state.
8. The electronic memory of claim 1 , further comprising a select transistor between the pass transistor and the serial array operable to isolate the gate of the pass transistor.
9. The electronic memory of claim 8 , further comprising a processing circuit that applies a shut-off voltage to the select transistor to isolate the gate of the pass transistor.
10. The electronic memory of claim 1 , further comprising an electrical contact at least in part composed of tungsten that couples the pass transistor with the second metal bitline.
11. The electronic memory of claim 1 , further comprising a processing circuit that applies a low voltage to the bitline and a higher voltage to the second metal bitline to independently program the one of the plurality of memory transistors.
12. The electronic memory of claim 1 , further comprising:
a processing circuit that applies a low bitline voltage for programming memory cells and a high bitline voltage to inhibit programming of memory cells; and
a plurality of serial arrays of memory transistors coupled at first respective ends thereof to respective metal bitlines of the electronic memory, wherein the processing circuit iteratively applies the low bitline voltage to respective subsets of the serial arrays to iteratively program selected memory cells of the respective subsets, and iteratively applies the high bitline voltage to inhibit programming of remaining serial arrays that are not part of the respective subsets.
13. The electronic memory of claim 1 , further comprising a processing circuit that applies a read voltage to the serial array to facilitate the sensing circuit determining the state of the one of the plurality of memory transistors.
14. The electronic memory of claim 13 , further comprising pre-charging the serial array and the gate of the pass transistor prior to application of the read voltage.
15. The electronic memory of claim 1 , the pass transistor enables or disables a current flow at the second bitline, wherein the current flow or lack thereof is determinative of the state of the cell.
16. The electronic memory of claim 1 , further comprising a select transistor that electrically connects or isolates the serial array with the gate of the pass transistor.
17. The electronic memory of claim 1 , comprising trench isolation lines formed into a first layer of a semiconductor substrate to electrically isolate the serial array of memory transistors from a second serial array of memory transistors.
18. The electronic memory of claim 17 , the second serial array having one end thereof connected to the second metal bitline, wherein programming or erasing the second serial array can be accomplished via a voltage applied at the second metal bitline.
19. The electronic memory of claim 18 , wherein programming or erasing the serial array can be accomplished via a second voltage applied at the metal bitline.
20. The electronic memory of claim 19 , further comprising a local interconnect at least in part comprised of tungsten for coupling the pass transistor to the serial array and a second local interconnect at least in part comprises of tungsten for coupling a second pass transistor to the second serial array.