High VT state used as erase condition in trap based nor flash cell design
View Patent ↗Aspects describe a system and method for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash device and the use of a high voltage state as an erased state. A default erased state can be a high voltage state. As a result, program operations can be performed by changing a voltage state of the single program and erase entity to a low voltage state, and erase operations can be performed by changing a voltage state of the single program and erase entity to a high voltage state.
1. A method of operating a flash device ( 100 ), comprising;
erasing a portion of or an entire of the flash memory by changing a voltage state of a single program and erase entity ( 402 ) of the flash device to a high voltage state, the single program and erase entity comprising two adjacent dual bit physical memory cells ( 404 , 406 ) of the flash memory as a single logical cell; and
programming the portion of or the entire of the flash memory by changing a voltage state of the single program and erase entity to a low voltage state.
2. The method of claim 1 , wherein changing the voltage state of the single program and erase entity to the high voltage state comprises:
applying an erase pulse to the portion of or the entire of the flash memory on the basis of the single program and erase entity.
3. The method of claim 1 , wherein erasing the flash device comprises:
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.
4. The method of claim 1 , wherein changing a voltage state of a single program and erase entity to a low voltage state comprises:
applying an program pulse to the portion of or the entire of the flash memory on the basis of the single program and erase entity.
5. The method of claim 1 , wherein programming the flash device comprises:
applying a hot-hole-injection gate voltage to a gate, applying a hot-hole-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
6. The method of claim 1 , wherein the memory cells comprising four or more data states.
7. The method of claim 1 , wherein the portion of or the entire of the flash device is erased with the proviso that a sector erase is not performed in the portion of or the entire of the flash memory.
8. The method of claim 1 , wherein the portion of or the entire of the flash memory is erased with the proviso that an erase pulse is not sequentially applied to two or more consecutive bitlines in the portion of or the entire of the flash memory.
9. A method of operating a flash device ( 100 ), comprising;
erasing a portion of or an entire of the flash device by trapping a charge in a single program and erase entity ( 402 ) on a basis of the single program and erase entity, the single program and erase entity comprising two adjacent dual bit memory cells ( 404 , 406 ) of the flash memory; and
programming the portion of or the entire of the flash memory by neutralizing a charge in the single program and erase entity on the basis of the single program and erase entity.
10. The method of claim 9 , wherein trapping the charge in the single program and erase entity on the basis of the single program and erase entity comprises:
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting at least one of non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.
11. The method of claim 9 , wherein neutralizing the charge in the single program and erase entity on the basis of the single program and erase entity comprises:
applying a hot-hole-injection gate voltage to a gate, applying a hot-hole-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
12. The method of claim 9 , wherein erasing does not comprise a soft-program cycle.
13. The method of claim 9 , wherein the portion of or the entire of the flash memory is erased with the proviso that a sector erase is not performed in the portion of or the entire of the flash memory.
14. The method of claim 9 , wherein the portion of or the entire of the flash memory is erased with the proviso that an erase pulse is not sequentially applied to two or more consecutive bitlines in the portion of or the entire of the flash memory.
15. A flash device ( 2500 ), comprising;
a plurality of single program and erase entities ( 2502 ) comprising two adjacent dual bit physical memory cells of the flash device; and
one or more decoders ( 2506 , 2508 ) that select one or more single program and erase entities for erasing the flash device on a basis of the single program and erase entity by changing a voltage state of single program and erase entities to a high voltage state.
16. The flash device of claim 15 , wherein the decoders comprises one or more bitline decoders that facilitate erasing a portion of or an entire of the flash device on the basis of the single program and erase entity with the proviso that a sector erase is not performed in the portion of or the entire of the flash memory.
17. The flash device of claim 15 , wherein the decoders comprises one or more bitline decoders that facilitate erasing a portion of or an entire of the flash device on the basis of the single program and erase entity with the proviso that an erase pulse is not sequentially applied to two or more consecutive bitlines in the portion of or the entire of the flash memory.
18. The flash device of claim 15 , wherein the decoders select one or more single program and erase entities with the proviso that the decoders does not select bitlines between the single program and erase entities for applying an erase bitline voltage.
19. The flash device of claim 15 , wherein the decoders select one or more single program and erase entities to erase the flash memory by applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting at least one of non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground.
20. The flash device of claim 15 , wherein the memory cells comprising four or more data states.