Methods for forming a memory cell having a top oxide spacer
View Patent ↗Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
1. A method for fabricating a semiconductor memory cell having a spacer layer comprising:
forming a plurality of source/drain regions in a substrate wherein said plurality of source/drain regions are formed between trenches;
forming a first oxide layer above said plurality of source/drain regions and in said trenches;
forming a charge storage layer above said first oxide layer;
separating said charge storage layer in said trenches wherein a space is formed between separated portions of said charge storage layer;
forming a spacer layer to fill said space between said separated portions of said charge storage layer and to rise a predetermined distance above said space;
forming a second oxide layer above said charge storage layer and above said spacer layer; and
forming a polysilicon layer above said second oxide layer.
2. The method of claim 1 wherein said forming a spacer layer comprises using material selected from the group that includes ALD, HARP, eHARP, HTO, TEOS, HDP, BPSG, SOG, and un-doped poly.
3. The method of claim 1 wherein said forming a spacer layer comprises performing a CMP and/or etch back of material formed above said source/drain regions and in said trenches.
4. The method of claim 1 wherein said charge storage layer is formed from SiRN.
5. The method of claim 1 wherein said separating said charge storage layer is performed by etching.
6. The method of claim 1 wherein said polysilicon layer is formed by deposition.
7. The method of claim 1 wherein said trenches comprise STI trenches.