Apparatus and method for generating wide-range regulated supply voltages for a flash memory
View Patent ↗A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
1. A circuit for flash memory voltage regulation, comprising:
a resistor ladder that is arranged to provide a plurality of resistor ladder output voltages;
a first multiplexer that is arranged to provide a coarse reference voltage by selecting one of the plurality of resistor ladder output voltages based on a coarse adjustment signal;
a first fine series regulator controller that is arranged to control regulation an output voltage employing the coarse reference voltage as a reference voltage for the regulation of the output voltage, such that a value of the regulated output voltage is based in part on the coarse reference voltage, and further based in part on a fine adjustment signal, wherein the fine series regulator controller includes an error amplifier having at least a first input that is arranged to receive the coarse reference voltage, and a second input;
a first resistor circuit that is coupled between the output node and the second input of the error amplifier; and
a first current source that is arranged to provide a first current to the first resistor circuit, such that the first current is proportional to the fine adjustment signal.
2. The circuit of claim 1 , further comprising:
a coarse series regulator controller, wherein the resistor ladder is coupled between a top resistor ladder voltage and a bottom resistor ladder voltage, the coarse series regulator controller is arranged to control regulation of the top resistor ladder voltage, and wherein the coarse series regulator controller is arranged to receive one of the resistor ladder output voltages as a feedback voltage for the series regulation of the top resistor ladder voltage.
3. The circuit of claim 1 ,
wherein the first resistor circuit consists of a plurality of resistors coupled in series with each other.
4. The circuit of claim 1 , further comprising:
a plurality of charge pumps, wherein each of the plurality of charge pumps has an output, each of the plurality of outputs of the charge pumps are coupled together at a charge pump output node, and wherein the first fine series regulator controller has a power supply input that is coupled to the charge pump output node.
5. The circuit of claim 1 , wherein
the resistor ladder includes means for providing the plurality of resistor ladder output voltages such that the plurality of resistor ladder output voltages are evenly spaced from each other; or
the first resistor circuit includes means for providing a fixed resistance across it.
6. The circuit of claim 1 , further comprising:
a second multiplexer that is arranged to provide a second coarse reference voltage by selecting one of the plurality of resistor ladder output voltage based on a second coarse adjustment signal;
a second fine series regulator controller that is arranged to control regulation a second output voltage employing the second coarse reference voltage as a reference voltage for the regulation of the second output voltage, such that a value of the regulated second output voltage is based in part on the second coarse reference voltage, and further based in part on a second fine adjustment signal, wherein the second fine series regulator controller includes a second error amplifier having at least a first input that is arranged to receive the coarse reference voltage, and a second input;
a second resistor circuit that is coupled between the output node and the second input of the second error amplifier; and
a second current source that is arranged to provide a second current to the second resistor circuit, such that the second current is proportional to the second fine adjustment signal.
7. The circuit of claim 6 , further comprising:
a plurality of flash memory core cells that are coupled to word lines and bit lines;
sense amplifiers; and
a memory controller, including decoder circuitry, wherein the memory controller arranged to provide a word line voltage to at least one of the word lines of plurality of flash memory cores cells employing the output voltage as the supply voltage for the word line voltage, the decoder circuitry is arranged to provide selected bit lines of the plurality of flash memory cores cells to the sense amplifiers during a read operation, and wherein the decoder circuitry employs the second output voltage as a supply voltage for the decoding.
8. A method for flash memory voltage regulation, comprising:
providing a plurality of voltages, wherein the plurality of voltages are distinct from each other;
selecting one of the plurality of voltages as a first coarse reference voltage employing a first coarse adjustment signal to make the selection;
employing a first fine series regulator to regulate a first output voltage employing the first coarse reference signal as a reference voltage for the regulation of the first output voltage, such that a value of the regulated first output voltage is based in part on the first coarse reference voltage, and further based in part on a first fine adjustment signal;
providing a first voltage drop between the output voltage and an input of the first series regulator such that the first voltage drop is proportional to the first fine adjustment signal.
9. The method of claim 8 , further comprising:
generating the plurality of voltages with a resistor ladder; and
providing a top voltage of the resistor ladder by performing coarse series regulation to generate the top voltage of the resistor ladder and employing one of the plurality of voltages as the feedback voltage for the coarse series regulation.
10. The method of claim 8 , further comprising:
selecting one of the plurality of voltages as a second coarse reference voltage employing a second coarse adjustment signal to make the selection;
employing a second fine series regulator to regulate a second output voltage employing the second coarse reference signal as a reference voltage for the regulation of the second output voltage, such that a value of the regulated second output voltage is based in part on the second coarse reference voltage, and further based in part on a fine adjustment signal;
providing a second voltage drop between the second output voltage and an input of the second series regulator such that the second voltage drop is proportional to the second fine adjustment signal.