Memory employing independent dynamic reference areas
A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.
1. A memory, comprising:
at least one word line;
a plurality of dynamic reference (Dref) cells coupled to the word line, wherein the plurality of Dref cells is arranged to form a first Dref area and a second Dref area;
a plurality of memory cells that is coupled to the word line, wherein the plurality of memory cells is arranged to form a data area that is positioned between the first Dref area and the second Dref area;
one or more sense amplifiers; and
a switch component that is arranged to receive addressing data, wherein the switch component is configured to independently couple one of the first Dref area or the second Dref area to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells in the plurality of memory cells along the word line.
2. The memory of claim 1 , wherein the sense amplifiers are arranged to sense a threshold voltage level associated with one or more memory cells in the data area during at least a portion of signal rise-up on the word line.
3. The memory of claim 1 , wherein the data area is arranged to provide an output signal, the first Dref area is arranged to provide at least two first reference signals, and the second Dref area is arranged to provide at least two second reference signals, and wherein the sense amplifiers are configured to provide read data by comparing the output signal with a signal that is based, at least in part, on the first reference signals or the second reference signals.
4. The memory of claim 1 , wherein the switch component is further configured to electrically isolate the second Dref area from the sense amplifiers while the first Dref area is coupled to the sense amplifiers, and wherein the switch component is also further configured to electrically isolate the first Dref area from the sense amplifiers while the second Dref area is coupled to the sense amplifiers.
5. The memory of claim 1 , wherein the memory further includes one or more reference cells, and wherein the switch component is further configured to couple the one or more reference cells to the sense amplifiers based on the addressing data.
6. The memory of claim 1 , further comprising:
one or more reference cells;
a plurality of cascode circuits coupled between the sense amplifiers and at least a portion of the plurality of memory cells;
a plurality of cascode circuit sets coupled between the sense amplifiers and at least a portion of the plurality of Dref cells; and
at least one cascode circuit coupled between the sense amplifiers and at least a portion of the reference cells.
7. The memory of claim 1 , wherein the first Dref area includes at least two Dref cells that are configured to provide at least two signals corresponding to a first set of threshold voltages, and wherein the second Dref area includes at least two Dref cells that are configured to provide at least two signals corresponding to a second set of threshold voltages.
8. The memory of claim 1 , wherein the plurality of memory cells includes dual-bit memory cells, and wherein each of the first Dref area and the second Dref area includes a memory cell corresponding to a “01” logic state and another memory cell corresponding to a “10” logic state.
9. The memory of claim 1 , wherein the word line is coupled to a decoder for selecting the word line amongst other word lines, wherein individual memory cells in the plurality of memory cells are coupled to corresponding bit lines, and wherein the individual bit lines are coupled to another decoder for selecting one or more of the individual bit lines.
10. The memory of claim 1 , further comprising:
means for coupling an individual memory cell in the plurality of memory cells to an individual sense amplifier; or
means for coupling two or more memory cells in the plurality of memory cells to the individual sense amplifier.
11. A method for sensing a logic state of one or more memory cells, the method comprising:
receiving addressing data;
selecting a word line by employing the addressing data to provide a control signal to a first dynamic reference (Dref) area coupled to the word line, a second Dref area coupled to the word line, and a data area coupled to the word line and positioned between the first Dref area and the second Dref area;
providing at least two reference signals from one of the first Dref area and the second ref area based on the addressing data; and
determining a logic state associated with at least one memory cell coupled to the word line in the data area based, at least in part, on the reference signals.
12. The method of claim 11 , wherein determining the logic state of the memory cell includes determining a threshold voltage level during at least a portion of signal rise-up on the word line.
13. The method of claim 11 , further comprising providing the reference signals from the first Dref area when the memory cell is located at a position that is closer to the first Dref area than the second Dref area.
14. The method of claim 12 , wherein determining the logic state includes:
providing an output signal corresponding to the memory cell; and
comparing the output signal to the threshold voltage level.
15. The method of claim 11 , further comprising:
selecting individual memory cells in the data area by providing the addressing data to one or more decoder circuits; and
selecting one of the first Dref area and the second Dref area by providing the addressing data to a switch control circuit.
16. The method of claim 11 , further comprising providing another reference signal from at least one reference cell that is separate from the first Dref area and the second Dref area of the arrayed memory, wherein determining the logic state is further based, at least in part, on the other reference signal.
17. The method of claim 11 , wherein the reference signals include a signal associated with a “01” logic state of a dual-bit memory cell and another signal associated with a “10” logic state of another dual-bit memory cell.
18. A semiconductor device, comprising:
at least one word line;
a plurality of Dref cells coupled to the word line, wherein the plurality of Dref cells is arranged to form a first Dref area and a second Dref area;
a plurality of memory cells coupled to the word line, wherein the plurality of memory cells is arranged to form a data area positioned between the first Dref area and the second Dref area;
one or more first sense amplifiers arranged to determine the logic state of memory cells associated with a portion of the data area based, at least in part, on at least two reference signals associated with the first Dref area; and
one or more second sense amplifiers arranged to determine the logic state of memory cells associated with another portion of the data area based, at least in part, on at least two other reference signals associated with the second Dref area.
19. The semiconductor device of claim 18 , wherein the first sense amplifiers and the second sense amplifiers are arranged to sense a threshold voltage level associated with one or more memory cells in the data area during at least a portion of signal rise-up on the word line.
20. The semiconductor device of claim 18 , further comprising:
one more reference cells that are arranged to provide another signal; and
a divider circuit that is arranged to receive the other signal and provide a portion of the other signal to the first sense amplifiers and another portion of the other signal to the second sense amplifiers.