EEPROM emulation in flash device
View Patent ↗Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device.
1. A method of emulating byte alterability in a flash device, comprising;
changing a voltage state in a single program and erase entity to a first voltage state on a basis of a single program and erase entity, the single program and erase entity comprising two adjacent dual bit physical memory cells of the flash device as a single logical cell; and
changing the voltage state in the single program and erase entity to a second voltage state that is different from the first voltage state,
wherein changing the voltage state in the single program and erase entity comprises:
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
2. The method of claim 1 , wherein changing the voltage state in the single program and erase entity further comprises:
applying a hot-electron-injection voltage or a hot-hole-injection voltage to a portion of or an entire of the flash memory on the basis of the single program and erase entity.
3. The method of claim 1 , wherein the memory cells comprise nitride dielectric charge trapping layers.
4. The method of claim 1 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not sequentially applied to two or more consecutive bitlines in the portion of or the entire of the flash device.
5. The method of claim 1 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not applied bitlines between the single program and erase entities.
6. The method of claim 1 , wherein changing the voltage state in the single program and erase entity is performed one or more times without a sector erase operation.
7. The method of claim 1 further comprising erasing the flash device by changing the voltage state to a predetermined voltage state on the basis of the single program and erase entity.
8. The method of claim 7 , wherein erasing the flash device comprises:
applying a hot-electron-injection voltage or a hot-hole-injection voltage to a portion of or an entire of the flash memory on the basis of the single program and erase entity to change the voltage state to the predetermined voltage state.
9. A method of emulating byte alterability in a flash device comprising a plurality of dual bit memory cells, comprising;
mapping two adjacent physical memory cells as a single program and erase entity; and
programming a portion of or an entire of the flash memory on a basis of the single program and erase entity,
wherein programming the flash device on the basis of the single program and erase entity comprises:
applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or
applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
10. The method of claim 9 , wherein programming the flash device on the basis of the single program and erase entity further comprises:
applying a program pulse to the portion of or the entire of the flash memory on the basis of the single program and erase entity.
11. The method of claim 9 , wherein the memory cells comprise nitride dielectric charge trapping layers.
12. The method of claim 9 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is applied to at most every other bitline and not sequentially applied to two or more consecutive bitlines in the portion of or the entire of the flash device.
13. The method of claim 9 , wherein the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage is not applied bitlines between the single program and erase entities.
14. The method of claim 9 , wherein programming the flash device on the basis of the single program and erase entity is performed one or more times without a sector erase operation.
15. The method of claim 9 further comprising erasing the flash device on the basis of the single program and erase entity to a predetermined voltage state.
16. A flash device that emulates an electrically eraseable programmable read only memory, comprising:
a plurality of single program and erase entities comprising two adjacent dual bit physical memory cells in the flash memory;
one or more bitline decoders and wordline decoders that select one or more single program and erase entities for operating the flash memory device on a basis of the single program and erase entity, the bitline decoders comprising a table driven decoder,
wherein the bitline decoders facilitate programming the flash device on the basis of the single program and erase entity by applying a hot-electron-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and connecting non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to ground; or applying a hot-hole-injection gate voltage to a gate, applying a hot-electron-injection bitline voltage to a common bitline of the single program and erase entity that is shared by the two adjacent dual bit physical memory cells, and allowing non-common bitlines of the single program and erase entity that are not shared by the two adjacent dual bit physical memory cells to float.
17. The flash device of claim 16 , wherein the bitline decoders further facilitate programming the flash device on the basis of the single program and erase entity by applying a program pulse to a portion of or an entire of the flash memory on the basis of the single program and erase entity.
18. The flash device of claim 16 , wherein the memory cells comprise nitride dielectric charge trapping layers.
19. The flash device of claim 16 , wherein the decoders comprises one or more bitline decoders that do not sequentially select two or more consecutive bitlines for applying the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage.
20. The flash device of claim 16 , wherein the decoders comprises one or more bitline decoders that do not select bitlines between the single program and erase entities for applying the hot-electron-injection bitline voltage or the hot-electron-injection bitline voltage.