HTO offset and BL trench process for memory device to improve device performance
View Patent ↗Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
1. A method of making memory cells, comprising:
providing features and first openings therebetween on a semiconductor substrate, the feature comprising a charge trapping dielectric stack and a poly gate;
forming pocket implant regions adjacent and under the charge trapping dielectric stack in the semiconductor substrate;
forming spacers adjacent side surfaces of the features and in the first openings, the spacers comprising oxides or nitrides;
forming bit line trenches between the spacers under the first openings that extend into the semiconductor substrate, thereby forming bit line openings; and
forming bit lines under the bit line openings in the semiconductor substrate.
2. The method of claim 1 , wherein forming bit lines comprises implantation of one or more dopants using the spacers as an implant screen.
3. The method of claim 1 , wherein forming the spacers comprises a high temperature oxide formation process.
4. The method of claim 1 , wherein the bit line is formed so that a portion of the bit line overlaps with a portion of the pocket implant region.
5. The method of claim 1 further comprising forming bit line dielectrics in the bit line openings.
6. The method of claim 1 further comprising forming bit line dielectrics in the bit line openings with the proviso that the spacers are not removed from the first openings.
7. The method of claim 6 , wherein the bit line dielectric and the spacer comprise the same material.
8. A method of increasing an effective channel length in memory cells, comprising:
providing features and first openings therebetween on a semiconductor substrate, the feature comprising a charge trapping dielectric stack and a poly gate;
forming pocket implant regions adjacent and under the charge trapping dielectric stack in the semiconductor substrate;
forming spacers adjacent side surfaces of the features, the spacers comprising oxides or nitrides;
forming bit line trenches between the spacers under the first openings in the semiconductor substrate, thereby forming bit line openings; and
forming bit lines under the bit line openings in the semiconductor substrate by using the spacers as an implant screen to constrain a length of the bit lines.
9. The method of claim 8 , wherein the spacer is formed by a high temperature oxide formation process.
10. The method of claim 8 , wherein the length of the bit line is constrained so that an effective channel length of the memory cell is about 70% or more and about 100% or less of the length of the poly gate.
11. The method of claim 8 , wherein the bit line is formed so that a portion of the bit line overlaps with a portion of the pocket implant region.
12. The method of claim 8 further comprising forming bit line dielectrics in the bit line openings.
13. The method of claim 8 further comprising forming bit line dielectrics in the bit line openings with the proviso that the spacers are not removed from the bit line openings.
14. The method of claim 1 , wherein a length of the bit lines is constrained so that an effective channel length of the memory cells is about 70% or more and about 100% or less of the length of the poly gate.
15. The method of claim 1 , wherein forming pocket implant regions comprises using boron as an implant.
16. The method of claim 1 , wherein the bit line trenches have a depth from about 10 nm to about 100 nm.
17. The method of claim 1 , wherein a length of the bit lines is constrained so that an effective channel length of the memory cells is about 80% or more and about 100% or less of the length of the poly gate.
18. The method of claim 8 , wherein forming pocket implant regions comprises using boron as an implant.
19. The method of claim 8 , wherein the bit line trenches have a depth from about 10 nm to about 100 nm.
20. The method of claim 8 , wherein the charge trapping dielectric stack comprises silicon nitride.