Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
View Patent ↗Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
1. A memory device comprising:
two or more memory cells on a semiconductor substrate, each memory cell comprising one or more charge storage nodes and a first poly gate;
bit line dielectrics between the memory cells, the bit line dielectrics extending into the semiconductor substrate;
first bit lines in the semiconductor substrate under the bit line openings; and
second bit lines in the semiconductor substrate under the bit line openings, the second bit lines having a higher concentration of dopants compared to a concentration of dopants of the first bit lines.
2. The memory device of claim 1 , wherein the first bit line has a concentration of dopants of about 1E16 atoms/cm 3 or more and about 1E18 atoms/cm 3 or less, and the second bit line has a concentration of dopants of about 1E18 atoms/cm 3 or more and about 1E21 atoms/cm 3 or less.
3. The memory device of claim 1 , wherein a depth of the second bit line is greater than a depth of the first bit line.
4. The memory device of claim 1 , wherein the first bit line has a depth of about 10 nm or more and about 150 nm or less, and the second bit line has a depth of about 30 nm or more and about 300 nm or less.
5. The memory device of claim 1 , wherein the charge storage nodes are separated by a central dielectric.
6. The memory device of claim 1 , wherein the charge storage node comprises nitrides.
7. The memory device of claim 1 , wherein the bit line dielectric comprises a high temperature oxide.
8. The memory device of claim 1 , wherein a width of the second bit line is smaller than a width of the first bit line.
9. The memory device of claim 1 , wherein the two or more memory cells are dual bit memory cells.
10. The memory device of claim 1 , wherein the charge storage node comprises a charge storage dielectric material.
11. A memory device comprising:
two or more memory cells on a semiconductor substrate, each memory cell comprising one or more charge storage nodes and a first poly gate, the charge storage nodes comprising a charge storage dielectric material;
bit line dielectrics between the memory cells, the bit line dielectrics extending into the semiconductor substrate;
first bit lines in the semiconductor substrate under the bit line openings; and
second bit lines in the semiconductor substrate under the bit line openings, the second bit lines having a higher concentration of dopants compared to a concentration of dopants of the first bit lines.
12. The memory device of claim 11 , wherein the first bit line has a concentration of dopants of about 1E16 atoms/cm 3 or more and about 1E18 atoms/cm 3 or less, and the second bit line has a concentration of dopants of about 1E18 atoms/cm 3 or more and about 1E21 atoms/cm 3 or less.
13. The memory device of claim 11 , wherein a depth of the second bit line is greater than a depth of the first bit line.
14. The memory device of claim 11 , wherein the first bit line has a depth of about 10 nm or more and about 150 nm or less, and the second bit line has a depth of about 30 nm or more and about 300 nm or less.
15. The memory device of claim 11 , wherein the charge storage nodes are separated by a central dielectric.
16. The memory device of claim 11 , wherein a width of the second bit line is smaller than a width of the first bit line.
17. The memory device of claim 11 , wherein the two or more memory cells are dual bit memory cells.
18. A cell phone comprising a memory device, the memory device comprising:
two or more memory cells on a semiconductor substrate, each memory cell comprising one or more charge storage nodes and a first poly gate, the charge storage nodes comprising a charge storage dielectric material;
bit line dielectrics between the memory cells, the bit line dielectrics extending into the semiconductor substrate;
first bit lines in the semiconductor substrate under the bit line openings; and
second bit lines in the semiconductor substrate under the bit line openings, the second bit lines having a higher concentration of dopants compared to a concentration of dopants of the first bit lines.
19. The cell phone of claim 18 , wherein the first bit line has a concentration of dopants of about 1E16 atoms/cm 3 or more and about 1E18 atoms/cm 3 or less, and the second bit line has a concentration of dopants of about 1E18 atoms/cm 3 or more and about 1E21 atoms/cm 3 or less.
20. The cell phone of claim 18 , wherein the first bit line has a depth of about 10 nm or more and about 150 nm or less, and the second bit line has a depth of about 30 nm or more and about 300 nm or less, and the two or more memory cells are dual bit memory cells.