Semiconductor memory device with stacked memory cell structure

1. A semiconductor device comprising:

a first memory cell comprising a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element;

a first memory layer comprising a plurality of first memory cells arranged in a plane;

a second memory cell comprising a non-volatile second variable resistance element that stores data by varying a resistance value and a selection diode that selects the second variable resistance element; and

a second memory layer provided with more than one such second memory cell arranged in a plane; wherein

a plurality of second memory layers is stacked over the first memory layer.

2. The semiconductor device according to claim 1 , wherein the second variable resistance element and the selection diode is stacked in the second memory cell in a stacking direction of the first memory layer and the second memory layer.

3. The semiconductor device according to claim 1 , wherein an area occupied by the second memory cell is smaller than an area occupied by the first memory cell.

4. The semiconductor device according to claim 1 , wherein

the second memory layer comprises:

a plurality of second bit lines; and

a plurality of second word lines provided in a direction intersecting the plurality of second bit lines; wherein

the second memory cell is provided in an intersection region of the plurality of second bit lines and the plurality of second word lines, one end of the second memory cell being coupled a second bit line and the other end of the second memory cell being coupled a second word line; and

a plurality of vertically adjacent second memory layers comprised in the plurality of second memory layers share either a second bit line or a second word line.

5. The semiconductor device according to claim 1 , wherein

the first memory cell comprises:

a selection transistor; and

a first variable resistance element coupled to a drain terminal or a source terminal of the selection transistor.

6. The semiconductor device according to claim 1 , further comprising:

a semiconductor substrate supporting the first memory layer and the second memory layer; wherein

at least part of the selection transistor is formed in the semiconductor substrate.

7. The semiconductor device according to claim 1 , wherein

the first memory layer comprises:

a selection transistor layer comprising the selection transistor; and

a first variable resistance element layer comprising the first variable resistance element, the first variable resistance element layer being formed over the selection transistor layer.

8. The semiconductor device according to claim 1 , wherein

the first memory layer comprises:

a plurality of first bit lines;

a plurality of first word lines provided in a direction intersecting the plurality of first bit lines; and

a plurality of source lines provided in a direction along the plurality of first bit lines; wherein

the first memory cell is provided in an intersection region of the first bit lines and the first word lines, one end of the first memory cell being coupled to a first bit line and the other end of the first memory cell being coupled to a source line; and

a plurality of adjacent first memory cells comprised in the plurality of first memory cells share a source line.

9. The semiconductor device according to claim 1 , wherein the selection diode is a Schottky diode comprising transition metal oxide and a metal electrode.

10. The semiconductor device according to claim 1 , wherein the first memory cell stores data comprising at least one of:

a boot program read when turning on the power; and

an operating system OS program.