IP Library Granted Patent US 7,901,955
Granted Patent B2
US 7,901,955 · App. 11/821,653 · Granted Mar 8, 2011

Method of constructing a stacked-die semiconductor structure

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Quick Facts
Patent No.
US 7,901,955
App. No.
11/821,653
Granted
Mar 8, 2011
Kind
B2
Abstract

In constructing a multi-die semiconductor device, a plurality of semiconductor die are provided. Each die is probe tested when it is part of a wafer. Flat contacts are connected to each die when it is part of a wafer. After wafer sawing, each die is tested in a test socket, using the contacts connected thereto. The die are then packaged in stacked relation to form the multi-die semiconductor device.

Claims (34)

1. A method of constructing a multi-die semiconductor device comprising:

providing an unenclosed first semiconductor die;

providing flat metal contacts having parallel sides and parallel top and bottom surfaces on the unenclosed first semiconductor die that extend through mold compound wherein the surfaces of the flat metal contacts lie in the same plane as the surfaces of the mold compound;

testing the unenclosed first semiconductor die in a test socket, with the flat metal contacts on the unenclosed first semiconductor die in contact with test probes of the test socket; and

providing the first semiconductor die in a package including at least a second semiconductor die in stacked relation with the first semiconductor die.

2. The method of claim 1 wherein the flat metal contacts are provided when the first semiconductor die is part of a wafer.

3. The method of claim 1 and further comprising probe testing the first semiconductor die when the first semiconductor die is part of a wafer.

4. A method of constructing a multi-die semiconductor device comprising:

providing a first semiconductor die;

providing flat metal contacts having parallel sides and parallel top and bottom surfaces connected to the first semiconductor die that extend through mold compound wherein the surfaces of the flat metal contacts lie in the same plane as the surface of the mold compound;

testing the first semiconductor die in a test socket, using the flat metal contacts connected to the first semiconductor die;

providing a second semiconductor die;

providing contacts connected to the second semiconductor die;

testing the second semiconductor die in a test socket using the flat metal contacts connected to the second semiconductor die; and

providing the first semiconductor die and second semiconductor die in stacked relation in a package.

5. The method of claim 4 wherein the flat metal contacts connected to the first semiconductor die are provided when the first semiconductor die is part of a wafer, and wherein the flat metal contacts connected to the second semiconductor die are provided when the second semiconductor die is part of a wafer.

6. The method of claim 5 wherein the flat metal contacts connected to the first and second semiconductor die are substantially flat contacts.

7. A method of constructing a multi-die semiconductor device comprising:

providing an unenclosed first semiconductor die which has been probe-tested as part of a wafer;

providing an unenclosed second semiconductor die which has been probe-tested as part of a wafer;

providing flat metal contacts having parallel sides and parallel top and bottom surfaces connected to the unenclosed first semiconductor die that extend through mold compound and flat metal contacts connected to the unenclosed second semiconductor die that extend through mold compound wherein the surfaces of the flat metal contacts lie in the same plane as the surfaces of the mold compound;

testing the unenclosed first semiconductor die in a test socket, using the flat metal contacts connected to the unenclosed first semiconductor die;

testing the unenclosed second semiconductor die in a test socket, using the flat metal contacts connected to the unenclosed second semiconductor die; and

providing the first semiconductor die and second semiconductor die in stacked relation in a package.

8. The method of claim 7 wherein the flat metal contacts connected to the first semiconductor die are provided when the first semiconductor die is part of a wafer, and wherein the flat metal contacts connected to the second semiconductor die are provided when the second semiconductor die is part of a wafer.

9. The method of claim 7 wherein the flat metal contacts connected to the first semiconductor die are substantially flat contacts on the first semiconductor die.

10. The method of claim 7 wherein the flat metal contacts are substantially flat contacts connected to the first semiconductor die by connecting members.

11. The method of claim 1 and further comprising said semiconductor device incorporated in a system.

12. The method of claim 11 wherein the system is selected from the group consisting of a hand-held device, a vehicle, and a computer.

13. A method of constructing a semiconductor device comprising:

providing an unenclosed semiconductor die;

providing flat metal contacts having parallel sides and parallel top and bottom surfaces on the unenclosed semiconductor die that extend through mold compound wherein the surfaces of the flat metal contacts lie in the same plane as the surface of the mold compound; and

testing the unenclosed semiconductor die in a test socket, with the flat metal contacts on the unenclosed semiconductor die in contact with test probes of the test socket.

14. The method of claim 13 wherein the flat metal contacts are provided when the semiconductor die is part of a wafer.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2007
From: GRUPEN-SHEMANSKY, MELISSA
To: SPANSION LLC
Reel/Frame 019515/0977 →