Faulty dangling metal route detection
View Patent ↗A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.
1. A fault detection system for discovery of dangling metal route errors in a semiconductor chip design comprising:
a partition component that separates the semiconductor chip design and identifies potential dangling metal route errors included in the design, wherein a dangling metal route error comprises a portion of a metal route, inadvertently created in the design, that extends from a connection point to a terminus of the metal route and can, by itself, generate a fault; and
an analysis component that determines, from the potential dangling metal route errors identified by the partition component, actual dangling metal routes, as designed in the semiconductor chip design, that exceed a predetermined limit.
2. The system of claim 1 , the predetermined limit is an allowed dangling metal length identified based at least upon the semiconductor chip design.
3. The system of claim 1 , the partition component focuses on the metal layers of the semiconductor chip design.
4. The system of claim 1 , the analysis component verifies dangling metal routes exceeding the predetermined limit against a predetermined set of exception cases.
5. The system of claim 4 further comprising a learning component that refines the allowable exception cases based at least in part upon feedback on from a user.
6. The system of claim 5 , the learning component employs a probabilistic and/or statistical-based analysis to refine the allowable exception cases.
7. The system of claim 1 , the analysis component comprises a first pass component and a second pass component.
8. The system of claim 7 , the first pass component compares the potential faulty dangling metal routes against the predetermined limit to determine actual faults.
9. The system of claim 8 , the second pass component determines the applicability of exception cases to the actual faults determined by the first pass component.
10. The system of claim 9 , the second pass component records faults outside the exception cases to a report file.
11. A method of detecting dangling metal faults in a semiconductor layout design comprising:
locating metal intersections on the semiconductor layout design; and
analyzing the metal intersections to discover dangling metal route errors created in the design, wherein a dangling metal route error includes a portion of a metal route, inadvertently created in the design, that extends from a connection point to a terminus of the metal route and can, by itself, generate a fault.
12. The method of claim 11 , further comprising reporting the discovered faulty dangling metal routes.
13. The method of claim 11 , locating metal intersections comprises ignoring non-metal layers of the semiconductor layout design.
14. The method of claim 11 , analyzing the metal intersections comprises comparing dangling metal route lengths to a layout specific length limit.
15. The method of claim 11 , further comprising verifying faulty dangling metal routes against exception cases to ensure actual violation.
16. The method of claim 15 , further comprising providing feedback information on actual violations to identify new exception cases.
17. The method of claim 16 , further comprising employing machine learning techniques to refine exceptions cases based at least upon the feedback information.
18. The method of claim 11 , further comprising providing a dangling length threshold for the semiconductor layout design above which a metal route is determined to be a fault.
19. A computer-readable medium that implements the method of claim 11 .
20. A system of detecting long dangling metal routes in a layout design, comprising:
means for identifying metal-on-metal intersections within the layout design;
means for comparing a length of a dangling metal route error, included in the design, to a predetermined limit, wherein the dangling metal route error includes a portion of the metal route, inadvertently created in the design, that extends beyond the metal-on-metal intersections and can, by itself, generate a fault; and
means for allowing the dangling metal route error when the length is beyond the limit when the dangling metal route error conforms to at least one case from a set of predetermined exceptional cases.