IP Library Granted Patent US 7,915,661
Granted Patent B2
US 7,915,661 · App. 12/543,404 · Granted Mar 29, 2011

Semiconductor device and fabrication method therefor

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Quick Facts
Patent No.
US 7,915,661
App. No.
12/543,404
Granted
Mar 29, 2011
Kind
B2
Abstract

The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches ( 11 ) formed in a semiconductor substrate ( 10 ), first ONO films ( 18 ) provided on both side surfaces of the trenches, and first word lines ( 22 ) provided on side surfaces of the first ONO films ( 18 ) and running in a length direction of the trenches ( 11 ). According to the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, in which higher memory capacity can be achieved.

Claims (47)

1. A semiconductor device comprising:

a semiconductor substrate;

trenches formed in said semiconductor substrate;

an ONO film comprising first ONO film portions that are formed in said trenches and second ONO film portions that are formed on the surface of said semiconductor substrate;

first word lines that are formed inside said trenches, wherein said first word lines extend in a direction that is parallel to respective side surfaces of said first ONO film portions and to respective side surfaces of said trenches; and

bit lines that are provided in said semiconductor substrate that extend in a direction that is orthogonal to the direction in which side surfaces of said trenches extend.

2. The semiconductor device of claim 1 , wherein said first ONO film portions and said second ONO film portions have charge storage regions.

3. The semiconductor device of claim 1 , wherein said first ONO film portions and said second ONO film portions have a shared trap layer.

4. The semiconductor device of claim 1 , wherein said first ONO film portions and said second ONO film portions have separate trap layers.

5. The semiconductor device of claim 1 , further comprising:

second word lines;

an interlayer insulation film provided above said second word lines and said trenches, wherein said interlayer insulation film comprises first contact holes for connecting said first word lines to a wiring layer.

6. The semiconductor device of claim 5 , wherein said first contact holes provide access to respective ones of said first word lines at different positions in a direction that is parallel to said side surfaces of said trenches.

7. The semiconductor device of claim 5 , wherein said interlayer insulation film comprises second contact holes that provide access to said second word lines wherein said second contact holes are formed at different positions from said first contact holes in a direction that is parallel to said side surfaces of said trenches.

8. The semiconductor device of claim 1 , wherein said first ONO film portions comprise portions that are formed on bottom surfaces of said trenches and wherein said first word lines form a single word line in said trenches.

9. The semiconductor device of claim 1 , wherein said first word lines are electrically isolated from each other in said trenches.

10. The semiconductor device of claim 9 , further comprising:

second word lines;

an interlayer insulation film provided above said second word lines and said trenches, wherein said interlayer insulation film comprises first contact holes for connecting said first word lines to a wiring layer.

11. The semiconductor device of claim 1 , wherein said first ONO film portions are coupled on said semiconductor substrate via said second ONO film portions between adjacent trenches to form a single ONO film.

12. The semiconductor device of claim 1 , further comprising trap layers formed in said first ONO film portions wherein said trap layers are formed on side surfaces of adjacent trenches and are isolated from each other.

13. A method of fabricating a semiconductor device comprising:

forming a semiconductor substrate;

forming trenches in said semiconductor substrate;

forming an ONO film comprising forming first ONO film portions in said trenches and forming second ONO film portions on the surface of said semiconductor substrate; and

forming first word lines inside said trenches to extend in a direction that is parallel to respective side surfaces of said first ONO film portions and to respective side surfaces of said trenches;

forming a second word line;

forming an interlayer insulation film above said second word line;

forming first contact holes in said interlayer insulation film that provide access to the top surfaces of said first word lines; and

forming a second contact hole for contacting said second word line at a position of said interlayer insulation film different from the positions of said first contact holes, in a direction that is parallel to said side surfaces of said trenches.

14. The method of claim 13 , wherein forming said ONO film comprises forming a shared trap layer for said first ONO film portions and said second ONO film portions.

15. The method of claim 14 , further comprising removing portions of said trap layer in said ONO film on said surface of said semiconductor substrate between said trenches.

16. The method of claim 13 , wherein forming said ONO film comprises forming trap layers for said first ONO film portions and said second ONO film portions in different operations.

17. The method of claim 16 , wherein forming said ONO film comprises forming a top silicon oxide film that is common to said first ONO film portions and said second ONO film portions.

18. The method of claim 13 , wherein said forming said first contact holes comprises forming respective contact holes for contacting each of a pair of first word lines located adjacent respective side surfaces of said trenches, wherein said respective first contact holes are formed at different positions in a direction that is parallel to said side surfaces of said trenches.

19. The method of claim 13 , wherein said forming said first word lines comprises:

forming a layer from which said first word lines are formed on side surfaces of said first ONO film portions and on said second ONO film portions that are located between said trenches, and

removing portions of said layer from which said first word lines are formed that are located between said trenches.

20. The method of claim 19 , wherein said forming said first word lines comprises forming a protect layer that is embedded between regions of said layer from which said first word lines are formed.

21. The method of claim 20 , wherein said removing portions of said layer from which said first word lines is formed comprises allowing said layer from which said first word lines is formed to remain on said side surfaces of said first ONO film portions at the same height as a top surface of said protect layer.

22. The method of claim 20 , further comprising removing said protect layer.

23. The method of claim 19 , wherein said removing portions of said layer from which said first word lines are formed includes removing portions of said layer from which said first word lines are formed by polishing.

24. The method of claim 13 , wherein said forming said first ONO film includes forming ONO film portions on both side surfaces said trenches, on the bottom surfaces of said trenches, and on said semiconductor substrate between said trenches.

25. The method of claim 13 , further comprising electrically isolating said first word lines from each other.

26. The method of claim 25 , further comprising:

forming and interlayer insulation film above said semiconductor substrate; and

forming first contact holes in said interlayer insulation film between said trenches for contacting top surfaces of said first word lines, wherein forming said first contact holes comprises forming respective ones of said first contact holes at a different position in a direction that is parallel to said trenches.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →