IP Library Granted Patent US 7,902,590
Granted Patent B2
US 7,902,590 · App. 12/004,919 · Granted Mar 8, 2011

Semiconductor device, method of controlling the same, and method of manufacturing the same

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Quick Facts
Patent No.
US 7,902,590
App. No.
12/004,919
Granted
Mar 8, 2011
Kind
B2
Abstract

The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Claims (22)

1. A system, including a semiconductor device, the semiconductor device comprising:

a semiconductor region located in a semiconductor layer formed on an isolating layer;

an ONO film on the semiconductor region;

a plurality of bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer;

a device isolating region on two different sides of the semiconductor region opposite from the sides on which the plurality of bit lines are located, the device isolating region being in contact with the isolating layer; and

a first voltage applying unit that is coupled to the semiconductor region;

wherein the semiconductor region is surrounded by the plurality of bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

2. The system as claimed in claim 1 , wherein the first voltage applying unit applies a voltage to the semiconductor region, so as to eliminate charges in a outer area of a distribution of charges after the charges are accumulated in the ONO film.

3. The system as claimed in claim 1 , wherein the first voltage applying unit applies a voltage to the semiconductor region, so as to eliminate charges accumulated in the ONO film.

4. The system as claimed in claim 1 , wherein the semiconductor layer includes a p-type semiconductor layer, and wherein the isolating layer includes a depletion layer formed on an n-type semiconductor layer.

5. The system as claimed in claim 4 , wherein the semiconductor device further comprises a second voltage applying unit that applies a voltage to the n-type semiconductor layer, so as to form the depletion layer.

6. The system as claimed in claim 1 , wherein the semiconductor device further comprises:

a plurality of word lines that are located on the ONO film and intersect with the plurality of bit lines,

wherein a plurality of charge accumulating regions are formed in the ONO film, the charge accumulating regions being located between the plurality of bit lines and below the plurality of word lines.

7. The system as claimed in claim 1 , the system further comprising:

a processor;

a cache; and

a user input component.

8. The system as recited in claim 7 wherein the system is a portable media player.

9. The system as recited in claim 7 wherein the system is a wireless communications device.

10. The system as recited in claim 7 wherein the system is a computing device.

11. The system as recited in claim 7 , wherein said memory is flash memory that comprises at least one memory cell operable to store more than one bit.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2008
From: HAYAKAWA, YUKIO
To: SPANSION LLC
Reel/Frame 020685/0761 →