IP Library Granted Patent US 7,934,051
Granted Patent B2
US 7,934,051 · App. 12/012,390 · Granted Apr 26, 2011

Program and erase disabling control of WPCAM by double controls

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Quick Facts
Patent No.
US 7,934,051
App. No.
12/012,390
Granted
Apr 26, 2011
Kind
B2
Abstract

The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

Claims (18)

1. A semiconductor device comprising: a plurality of memory regions that include nonvolatile memory cells; a plurality of program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

2. The semiconductor device as claimed in claim 1 , wherein the first prohibition information control circuit prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region when the first prohibition information indicates a prohibition of a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region regardless of the second prohibition information.

3. The semiconductor device as claimed in claim 1 , further comprising:

an input terminal that inputs auxiliary program prohibition information to be used for determining whether to allow a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region,

wherein, when the second prohibition information allows a change of the memory cell from a program allowed state to a program prohibited state, and auxiliary information nullifying information to be used for determining whether to nullify the auxiliary program prohibition information indicates that the auxiliary program prohibition information is valid, the second prohibition information control circuit allows or does not allow a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on the auxiliary program prohibition information, and when the second prohibition information allows the change and the auxiliary information nullifying information indicates that the auxiliary program prohibition information is invalid, the second prohibition information control circuit allows a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, regardless of the auxiliary program prohibition information, and

wherein, the second prohibition information control circuit prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region when the second prohibition information indicates a prohibition of the memory cell from a program allowed state to a program prohibited state, regardless of the auxiliary program prohibition information and the auxiliary information nullifying information.

4. The semiconductor device as claimed in claim 1 , further comprising a second prohibition information memory that stores the second prohibition information.

5. The semiconductor device as claimed in claim 4 , wherein the program prohibition information units use a different command from a command used by the second prohibition information memory.

6. The semiconductor device as claimed in claim 4 ,

wherein the program prohibition information units are disposed on a first well in a semiconductor substrate, and

wherein the second prohibition information memory is provided on a second well in the semiconductor substrate, the second well being isolated from the well.

7. The semiconductor device as claimed in claim 4 , further comprising

a first prohibition information memory that stores the first prohibition information,

wherein the first prohibition information memory uses a different command from a command used by the second prohibition information memory.

8. A semiconductor device comprising: a plurality of memory regions that include nonvolatile memory cells; a plurality of program prohibition information units that are provided for the respective memory regions, each of the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in each corresponding one of the memory regions; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, wherein, when the first prohibition information allows a change of the memory region from a program prohibited state to a program allowed state, the first prohibition information control circuit allows or does not allow a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region, based on fourth prohibition information to be used for determining whether to allow a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region, and wherein, when the first prohibition information prohibits a change of the memory region from a program prohibited state to a program allowed state, the first prohibition information control circuit prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region, regardless of the fourth prohibition information.

9. The semiconductor device as claimed in claim 8 , wherein the second prohibition information control circuit allows or does not allow a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region when the second prohibition information allows a change of the memory region from a program allowed state to a program prohibited state, based on third prohibition information to be used for determining whether to allow a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, and

wherein, the second prohibition information control circuit prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region when the second prohibition information prohibits a change of the memory region from a program allowed state to a program prohibited state regardless of the third prohibition information.

10. A method for controlling a semiconductor device that includes a plurality of memory regions having nonvolatile memory cells, the method comprising: prohibiting a change of program prohibiting information from a program prohibiting state to a program allowing state with respect to a corresponding one of the memory regions, based on first prohibiting information to be used for determining whether to prohibit a change of the program prohibiting information from a program prohibiting state to a program allowing state with respect to the corresponding memory region, the program prohibiting information used to determine whether to prohibit or allow programming in each corresponding one of the memory regions; and prohibiting a change of the program prohibiting information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibiting information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2008
From: SHIBATA, KENJI; OKURA, MASAHIKO; NAGAO, MITSUHIRO
To: SPANSION LLC
Reel/Frame 020888/0807 →