Patent Assignment
Reel/Frame 034715/0305
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL
Recorded: 2014-12-30
Received: 2014-12-30
Pages: 29
Assignor
BARCLAYS BANK PLC
Executed: 2014-12-27
Assignees
SPANSION LLC
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION INC.
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION TECHNOLOGY INC.
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
SPANSION TECHNOLOGY LLC
915 DEGUIGNE DRIVE, SUNNYVALE, CA, 94088, UNITED STATES
Covered Applications
(100)
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 14/228,384
→
DATA WRITING METHOD AND SYSTEM
App. No. 14/149,484
→
DIELECTRIC COUPLING SYSTEMS FOR EHF COMMUNICATIONS
App. No. 13/963,199
→
ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY
App. No. 13/886,507
→
PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
App. No. 13/709,479
→
HARDWARE BASED WEAR LEVELING MECHANISM FOR FLASH MEMORY USING A FREE LIST
App. No. 13/670,910
→
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 13/668,935
→
PLL CIRCUIT
App. No. 13/558,835
→
ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY
App. No. 13/531,282
→
MULTIPLE COMMUNICATION CHANNELS ON MMC OR SD CMD LINE
App. No. 13/410,630
→
PACKET COMMUNICATION DEVICE FOR COMMUNICATING PACKET TO BE TRANSFERRED THROUGH PACKET COMMUNICATION WHICH IS TIME-MANAGED IN CONSTANT CYCLE AND PACKET COMMUNICATION METHOD THEREOF
App. No. 13/313,565
→
ELECTRONIC DEVICE, CONTROL CIRCUIT, AND METHOD FOR CONTROLLING LIGHT EMITTING ELEMENT
App. No. 13/305,684
→
PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM)
App. No. 13/301,826
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 13/252,714
→
DATA WRITING METHOD AND SYSTEM
App. No. 13/070,186
→
PLL CIRCUIT
App. No. 12/917,219
→
TIMING CONTROLLER, TIMING CONTROL METHOD, AND TIMING CONTROL SYSTEM
App. No. 12/817,692
→
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
App. No. 12/773,232
→
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 12/729,905
→
ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
App. No. 12/723,589
→
CHARGING CIRCUIT, CHARGING APPARATUS, ELECTRONIC EQUIPMENT AND CHARGING METHOD
App. No. 12/697,879
→
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
App. No. 12/646,279
→
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 12/646,291
→
DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD
App. No. 12/635,148
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 12/556,408
→
REGULATOR CIRCUIT
App. No. 12/535,184
→
CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE
App. No. 12/473,081
→
PACKET COMMUNICATION DEVICE FOR COMMUNICATING PACKET TO BE TRANSFERRED THROUGH PACKET COMMUNICATION WHICH IS TIME-MANAGED IN CONSTANT CYCLE AND PACKET COMMUNICATION METHOD THEREOF
App. No. 12/434,415
→
METHOD AND DEVICE FOR TRANSMITTING PACKETS
App. No. 12/385,002
→
TRANSMITTING/RECEIVING SYSTEM, NODE AND COMMUNICATION METHOD
App. No. 12/410,086
→
POWER-ON DETECTION CIRCUIT AND MICROCONTROLLER
App. No. 12/392,674
→
NON-VOLATILE MEMORY CELL WITH INJECTOR
App. No. 12/318,789
→
RETENTION IN NVM WITH TOP OR BOTTOM INJECTION
App. No. 12/318,767
→
SPI ADDRESSING BEYOND 24-BITS
App. No. 12/277,911
→
OPERATION OF A NON-VOLATILE MEMORY ARRAY
App. No. 12/292,240
→
SYSTEMS AND METHODS FOR ENHANCING A DATA STORE FOR HANDLING SEMANTIC INFORMATION
App. No. 12/270,616
→
MINIMIZING READ DISTURB IN AN ARRAY FLASH CELL
App. No. 12/232,418
→
PRE-CHARGE SENSING SCHEME FOR NON-VOLATILE MEMORY (NVM)
App. No. 12/232,437
→
RD ALGORITHM IMPROVEMENT FOR NROM TECHNOLOGY
App. No. 12/087,594
→
ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY
App. No. 12/139,650
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF
App. No. 12/139,274
→
COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE
App. No. 12/138,307
→
SHADOW WRITE AND TRANSFER SCHEMES FOR MEMORY DEVICES
App. No. 12/137,443
→
NONVOLATILE MEMORY DEVICE AND METHOD TO CONTROL THE SAME
App. No. 12/060,710
→
FLASH MEMORY AND OPERATING SYSTEM KERNEL
App. No. 12/059,816
→
DATA RECOVERY CIRCUIT
App. No. 12/047,856
→
METHOD, SYSTEM AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
App. No. 12/071,749
→
PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
App. No. 12/026,302
→
WEAR LEVELING MECHANISM USING A DRAM BUFFER
App. No. 12/026,299
→
NROM FABRICATION METHOD
App. No. 12/005,323
→
SYSTEM AND METHOD FOR OPTIMIZED ERROR CORRECTION IN FLASH MEMORY ARRAYS
App. No. 11/963,078
→
EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN
App. No. 11/960,601
→
INTELLIGENT MEMORY DATA MANAGEMENT
App. No. 11/957,226
→
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
App. No. 11/953,689
→
DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
App. No. 11/949,521
→
PLL CIRCUIT
App. No. 11/987,003
→
METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE
App. No. 11/984,152
→
REDUCTION OF PACKAGE HEIGHT IN A STACKED DIE CONFIGURATION
App. No. 11/983,041
→
NROM FRABRICATION METHOD
App. No. 11/979,183
→
ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
App. No. 11/928,434
→
LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE
App. No. 11/877,497
→
OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
App. No. 11/874,001
→
RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS
App. No. 11/870,102
→
CMOS LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL STRUCTURE, OPERATION, AND ARRAY CONFIGURATION
App. No. 11/841,468
→
READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
App. No. 11/834,420
→
COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES
App. No. 11/767,622
→
STATE CHANGE SENSING
App. No. 11/687,487
→
MEMORY ARRAY PROGRAMMING CIRCUIT AND A METHOD FOR USING THE CIRCUIT
App. No. 11/704,908
→
BYTE MASK COMMAND FOR MEMORIES
App. No. 11/625,158
→
METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
App. No. 11/653,655
→
SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
App. No. 11/618,075
→
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 11/644,161
→
SYSTEMS AND METHODS FOR DISTINGUISHING BETWEEN ACTUAL DATA AND ERASED/BLANK MEMORY WITH REGARD TO ENCRYPTED DATA
App. No. 11/615,492
→
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 11/644,031
→
NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
App. No. 11/614,257
→
SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
App. No. 11/614,309
→
NEAR FIELD COMMUNICATION, SECURITY AND NON-VOLATILE MEMORY INTEGRATED SUB-SYSTEM FOR EMBEDDED PORTABLE APPLICATIONS
App. No. 11/613,620
→
MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
App. No. 11/613,691
→
SECURE DATA VERIFICATION VIA BIOMETRIC INPUT
App. No. 11/613,627
→
SYSTEM AND METHOD FOR MAINTAINING RAM COMMAND TIMING ACROSS PHASE-SHIFTED TIME DOMAINS
App. No. 11/642,412
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 11/636,155
→
NONVOLATILE SEMICONDUCTOR MEMORY HAVING VOLTAGE ADJUSTING CIRCUIT
App. No. 11/607,090
→
USING SHARED MEMORY WITH AN EXECUTE-IN-PLACE PROCESSOR AND A CO-PROCESSOR
App. No. 11/557,439
→
REGULATOR CIRCUIT
App. No. 11/589,140
→
METHOD FOR PROGRAMMING A REFERENCE CELL
App. No. 11/518,192
→
MULTIPLE COMMUNICATION CHANNELS ON MMC OR SD CMD LINE
App. No. 11/469,755
→
PLL CIRCUIT AND SEMICONDUCTOR DEVICE
App. No. 11/505,446
→
RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY
App. No. 11/497,597
→
DYNAMIC MATCHING OF SIGNAL PATH AND REFERENCE PATH FOR SENSING
App. No. 11/490,539
→
METHOD FOR PROGRAMMING A REFERENCE CELL
App. No. 11/413,962
→
MULTI MEDIA CARD WITH HIGH STORAGE CAPACITY
App. No. 11/400,902
→
METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
App. No. 11/328,015
→
METHOD, SYSTEM, AND CIRCUIT FOR OPERATING A NON-VOLATILE MEMORY ARRAY
App. No. 11/324,718
→
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SAID SEMICONDUCTOR DEVICE
App. No. 11/290,001
→
NON-VOLATILE MEMORY DEVICE
App. No. 11/259,874
→
FLASH MEMORY PROGRAMMING USING AN INDICATION BIT TO INTERPRET STATE
App. No. 11/229,664
→
VOLTAGE REGULATOR WITH LESS OVERSHOOT AND FASTER SETTLING TIME
App. No. 11/212,614
→
COMMUNICATION DATA CONTROLLER
App. No. 11/169,747
→
METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
App. No. 11/037,477
→
METHOD FOR OPERATING A MEMORY DEVICE
App. No. 11/029,380
→